SC16C852VIET,115 NXP Semiconductors, SC16C852VIET,115 Datasheet - Page 40

• Manufacturer Part Number: SC16C852VIET,115
• Description: IC UART DUAL W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIET,115

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 36-TFBGA
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282518115; SC16C852VIET-G; SC16C852VIET-G

NXP Semiconductors
10. Dynamic characteristics
Table 39.
T
[1]
[2]
[3]
SC16C852V
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
XTAL1
d(CS-LLAH)
su(A-LLAH)
w(LLA)
h(LLAH-A)
d(IOW)
d(IOR-DV)
w(IOR)
d(LLAH-IORL)
w(IOW)
h(IOWH-D)
d(LLAH-IOWL)
su(D-IOWH)
d(IOR)
dis(IOR-QZ)
d(IOW-Q)
d(modem-INT)
d(IOR-INTL)
WH
WL
w(clk)
d(stop-INT)
d(stop-RXRDY)
d(IOR-RXRDYH)
d(start-INT)
d(IOW-TX)
d(IOW-INTL)
d(IOW-TXRDYH)
d(start-TXRDY)
w(RESET_N)
amb
External clock only; maximum crystal frequency is 24 MHz.
10 % of the data bus fall or rise time.
RCLK is an internal frequency and it is equal to 16 times the baud rate.
=
−
40
°
Dynamic characteristics
C to +85
Parameter
frequency on pin XTAL1
delay time from CS to LLA HIGH
set-up time from address to LLA HIGH
LLA pulse width time
address hold time after LLA HIGH
IOW delay time
delay time from IOR to data valid
IOR pulse width time
delay time from LLA HIGH to IOR LOW
IOW pulse width time
data input hold time after IOW HIGH
delay time from LLA HIGH to IOW LOW
set-up time from data input to IOW HIGH
IOR delay time
disable time from IOR to high-impedance data
output
delay time from IOW to data output
delay time from modem to INT
delay time from IOR to INT LOW
pulse width HIGH
pulse width LOW
clock pulse width
delay time from stop to INT
delay time from stop to RXRDY
delay time from IOR to RXRDY HIGH
delay time from start to INT
delay time from IOW to TX
delay time from IOW to INT LOW
delay time from IOW to TXRDY HIGH
delay time from start to TXRDY
pulse width on pin RESET
°
C; V
[2]
DD
= 1.65 V to 1.95 V; unless otherwise specified.
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 January 2011
25 pF load
25 pF load
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
[1]
[3]
[3]
[3]
[3]
Min
-
10
5
10
10
10
-
20
10
10
5
10
5
10
-
-
-
-
6
6
12.5
-
-
-
-
8T
-
-
-
10
RCLK
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SC16C852V
© NXP B.V. 2011. All rights reserved.
Max
80
-
-
-
-
-
40
-
-
-
-
-
-
-
20
50
50
50
-
-
-
1T
1T
50
1T
24T
50
50
8T
-
RCLK
RCLK
RCLK
RCLK
RCLK
40 of 55
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
ns
s
s
ns
ns
s
ns