SC16C750BIB64,128 NXP Semiconductors, SC16C750BIB64,128 Datasheet - Page 6

• Manufacturer Part Number: SC16C750BIB64,128
• Description: IC UART 64BYTE 64LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C750BIB64,128

• Number Of Channels: 1, UART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274403128; SC16C750BIB64-F; SC16C750BIB64-F

NXP Semiconductors
Table 2.
SC16C750B_5
Product data sheet
Symbol
CTS
D7 to D0
DCD
DDIS
DSR
DTR
INT
n.c.
OUT1,
OUT2
OUT
Pin description
Pin
PLCC44 LQFP64
40
9, 8, 7,
6, 5, 4,
3, 2
42
26
41
37
33
34
38, 35
-
33
52, 51, 50,
48, 46, 45,
43, 42
36
12
35
28
23
3, 5, 7, 11,
14, 16, 19,
22, 24, 27,
29, 31, 34,
37, 39, 41,
44, 47, 49,
53, 56, 57,
60, 63
30, 25
-
…continued
HVQFN32
25
3, 2, 1, 32,
31, 30,
29, 28
-
-
26
22
20
12
-
23
Type
I
I/O
I
O
I
O
O
-
O
O
Rev. 05 — 17 October 2008
Description
Clear to send. CTS is a modem status signal. Its condition can be
checked by reading bit 4 (CTS) of the Modem Status Register
(MSR). MSR[3] ( CTS) indicates that CTS has changed states
since the last read from the MSR. If the modem status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not
enabled, an interrupt is generated. CTS is also used in the
auto-CTS mode to control the transmitter.
Data bus. Eight data lines with 3-state outputs provide a
bidirectional path for data, control and status information between
the UART and the CPU.
Data carrier detect. DCD is a modem status signal. Its condition
can be checked by reading bit 7 (DCD) of the Modem Status
Register (MSR). MSR[3] ( DCD) indicates that DCD has changed
states since the last read from the MSR. If the modem status
interrupt is enabled when DCD changes levels, an interrupt is
generated.
Driver disable. DDIS is active (LOW) when the CPU is reading
data. When inactive (HIGH), DDIS can disable an external
transceiver.
Data set ready. DSR is a modem status signal. Its condition can be
checked by reading bit 5 (DSR) of the Modem Status Register. Bit 1
(DDSR) of the MSR indicates DSR has changed levels since the
last read from the MSR. If the modem status interrupt is enabled
when DSR changes levels, an interrupt is generated.
Data terminal ready. When active (LOW), DTR informs a modem
or data set that the UART is ready to establish communication. DTR
is placed in the active level by setting the DTR bit of the Modem
Control Register. DTR is placed in the inactive level either as a
result of a Master Reset, during Loopback mode operation, or
clearing the DTR bit.
Interrupt. When active (HIGH), INT informs the CPU that the UART
has an interrupt to be serviced. Four conditions that cause an
interrupt to be issued are: a receiver error, received data that is
available or timed out (FIFO mode only), an empty transmitter
holding register or an enabled modem status interrupt. INT is reset
(deactivated) either when the interrupt is serviced or as a result of a
Master Reset.
not connected
Outputs 1 and 2. These are user-designated output terminals that
are set to the active (LOW) level by setting respective Modem
Control Register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2
are set to inactive the (HIGH) level as a result of Master Reset,
during Loopback mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the MCR.
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
SC16C750B
© NXP B.V. 2008. All rights reserved.
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