SI3452MS8-EVB Silicon Laboratories Inc, SI3452MS8-EVB Datasheet - Page 14

• Manufacturer Part Number: SI3452MS8-EVB
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3452MS8-EVB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Si3452MS8-EVB
7. Board Schematics, BOM, and Layout
The following are general PCB layout considerations. Detailed schematics, BOM, and layout can also be found in
the following sections. Visit the Silicon Labs Technical Support web page and register to submit a technical support
request, particularly if you are not closely following the recommended reference design.
7.1. Design and Layout Considerations
Due to the high current of up to 800 mA per port, the following board layout guidelines apply.
The VEE1, VEE2, VEE3, and VEE4 pins can carry up to 800 mA and are connected to a VEE bus. The VEE bus
for a 4-port PCB layout can thus carry as much as 3.2 A current. The best practice is to devote an entire inner layer
for VEE power routing.
Similarly, GND1/2 and GND3/4 pins can carry up to 1.6 A per pin, and the GND return bus should be at least as
wide as the VEE bus. The best practice is to devote an entire inner layer for ground power routing.
The ground power plane does not generally have a high frequency content (other than external faults); so, it is
generally acceptable to use the ground power plane as a ground signal plane and tie AGND and GND12 and
GND34 to this plane as well.
The VOUTn pins carry up to 800 mA dc and up to 5 A in faults; so, a 20 mil trace with wide or multiple vias is also
recommended. The VDETn pins also carry fault current; so, this pin connection to VOUTn needs to use 20 mil
traces and wide or multiple vias where needed.
The VDD currents are not large; so, it is acceptable to route the VDD nodes on one of the outer layers. If care is
taken to avoid disruption of the high-current paths, VDD can be globally routed on one of the power planes and
then locally routed on an inner or outer layer.
To avoid coupling between surge events and logic signals, it is recommended that VOUTn traces be routed on the
2
side opposite the I
C interface pins.
The thermal pad of the Si3452/3 is connected to VEE. At full IEEE 802.3at and a current of 600 mA on each port,
the dissipation of the Si3452/3 is up to 1.2 W; so, multiple vias are required to conduct the heat from the thermal
pad to the VEE plane. As many as 36 small vias provide the best thermal conduction. Heat is dissipated through
the Si3452 by vias to a large Vee plane on the back of the board. Chip-to-chip spacing should be kept to greater
than one inch to reduce peak temperatures associated with the Si3452 chips from heating each other.
2
2
The I
C bus runs at a modest speed of 400 kHz maximum. The I
C bus lines should be routed away from analog
lines like Rbias or Vref but can otherwise be routed with ordinary care.
For the Si3452 itself, there are no EMI considerations. The Si3500 dc-to-dc converter in the reference design is a
potential EMI source; so, care must be used in routing the FET output (SWO). The lead lengths should be kept
short, and SWO should be kept away from the analog nodes. Also, the area enclosed by the paths between the
input filter caps to the inductor and returning to SWO and Vss and also from the output filter caps to the inductor
and returning through the diode should be minimized. Following the reference design closely in this area will insure
success.
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Rev. 0.4