SC16C852LIET,157 NXP Semiconductors, SC16C852LIET,157 Datasheet - Page 17
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SC16C852LIET,157
Manufacturer Part Number
SC16C852LIET,157
Description
IC UART DL 1.8V W/FIFO 36-TFBGA
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C852LIBS151.pdf
(64 pages)
Specifications of SC16C852LIET,157
Features
Programmable
Number Of Channels
2, DUART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
1.8V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
36-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935285388157
SC16C852LIET
SC16C852LIET
SC16C852LIET
SC16C852LIET
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C852LIET,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC16C852L
Product data sheet
6.9 Programmable baud rate generator
The SC16C852L UART contains a programmable rational baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (2
SC16C852L offers the capability of dividing the input frequency by rational divisor. The
fractional part of the divisor is controlled by the CLKPRES register in the ‘first extra feature
register set’.
where:
Prescaler = 1 when MCR[7] is set to 0.
Prescaler = 4 when MCR[7] is set to 1.
A single baud rate generator is provided for the transmitter and receiver. The
programmable Baud Rate Generator is capable of operating with a frequency of up to
80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock
input. The SC16C852L can be configured for internal or external clock operation. For
internal clock operation, an industry standard crystal is connected externally between the
XTAL1 and XTAL2 pins (see
to the XTAL1 pin (see
custom rates (see
The generator divides the input 16 clock by any divisor from 1 to (2
SC16C852L divides the basic external clock by 16. The baud rate is configured via the
CLKPRES, DLL and DLM internal register functions. Customized baud rates can be
achieved by selecting the proper divisor values for the MSB and LSB sections of the baud
rate generator.
Programming the baud rate generator registers CLKPRES, DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
shows the selectable baud rate table available when using a 1.8432 MHz external clock
input when MCR[7] = 0, and CLKPRES = 0x00.
baud rate
Fig 7.
N is the integer part of the divisor in DLL and DLM registers;
M is the fractional part of the divisor in CLKPRES register;
f
XTAL1
XTAL1
XTAL2
is the clock frequency at XTAL1 pin.
Prescalers and baud rate generator block diagram
=
OSCILLATOR
------------------------------------------------------------------ -
MCR 7
All information provided in this document is subject to legal disclaimers.
Table
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
Figure
Rev. 4 — 1 February 2011
f
XTAL1
7).
16
DIVIDE-BY-1
DIVIDE-BY-4
Figure
9) to clock the internal baud rate generator for standard or
N
+
----- -
16
M
8). Alternatively, an external clock can be connected
MCR[7] = 0
MCR[7] = 1
GENERATOR
BAUD RATE
(DLL, DLM)
CLKPRES
[3:0]
SC16C852L
16
1). The
© NXP B.V. 2011. All rights reserved.
16
1). The
transmitter and
receiver clock
002aac645
Table 7
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