SC16C852VIBS,557 NXP Semiconductors, SC16C852VIBS,557 Datasheet - Page 27

• Manufacturer Part Number: SC16C852VIBS,557
• Description: IC UART DUAL W/FIFO 48-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C852VIBS,557

• Features: Programmable
• Number Of Channels: 2, DUART
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283102557; SC16C852VIBS; SC16C852VIBS

NXP Semiconductors
SC16C852V
Product data sheet
7.4 Interrupt Status Register (ISR)
The SC16C852V provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits.
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 14.
Table 15.
Priority
level
1
2
2
3
4
5
6
Bit
7:6
5:4
3:1
0
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
0
0
0
0
0
0
1
Interrupt source
Interrupt Status Register bits description
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
0
0
0
0
0
1
0
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
Description
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C852V mode.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
interrupt priority levels 1, 2, and 3 (see
INT status.
Rev. 5 — 21 January 2011
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
0
0
1
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
Table 14 “Interrupt source”
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xoff signal)/
Special character
CTS, RTS change of state
Table
14).
SC16C852V
© NXP B.V. 2011. All rights reserved.
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