SC16C850LIET,115 NXP Semiconductors, SC16C850LIET,115 Datasheet - Page 39

• Manufacturer Part Number: SC16C850LIET,115
• Description: IC UART SINGLE W/FIFO 36TFBGA
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16C850LIET,115

• Number Of Channels: 1, UART
• Package / Case: 36-TFBGA
• Features: Programmable
• Fifo's: 128 Byte
• Protocol: RS485
• Voltage - Supply: 1.8V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 1.95 V
• Supply Voltage (min): 1.65 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935282854115; SC16C850LIET-G; SC16C850LIET-G

NXP Semiconductors
10. Dynamic characteristics
Table 37.
T
[1]
[2]
[3]
[4]
SC16C850L
Product data sheet
Symbol
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
N
WH
WL
w(clk)
XTAL1
su(A)
h(A)
d(CS-IOR)
w(IOR)
h(IOR-CS)
d(IOR)
d(IOR-Q)
dis(IOR-QZ)
d(CSL-IOWL)
w(IOW)
h(IOW-CS)
d(IOW)
su(D-IOWH)
h(IOWH-D)
d(IOW-Q)
d(modem-INT)
d(IOR-INTL)
d(stop-INT)
d(start-INT)
d(IOW-TX)
d(IOW-INTL)
w(RESET)
amb
Applies to external clock, crystal oscillator max 24 MHz.
Maximum frequency =
10 % of the data bus output voltage level.
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
=

40

Dynamic characteristics - Intel or 16 mode
C to +85
Parameter
pulse width HIGH
pulse width LOW
clock pulse width
frequency on pin XTAL1
address set-up time
address hold time
delay time from CS to IOR
IOR pulse width time
hold time from IOR to chip select
IOR delay time
delay time from IOR to data output
disable time from IOR to high-impedance
data output
delay time from CS LOW to IOW LOW
IOW pulse width time
hold time from IOW to CS
IOW delay time
set-up time from data input to IOW HIGH
data input hold time after IOW HIGH
delay time from IOW to data output
delay time from modem to INT
delay time from IOR to INT LOW
delay time from stop to INT
delay time from start to INT
delay time from IOW to TX
delay time from IOW to INT LOW
pulse width on pin RESET
baud rate divisor

C; V
-------------- -
t
w clk
DD
[3]

1
= 1.65 V to 1.95 V; unless otherwise specified.

All information provided in this document is subject to legal disclaimers.
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
Rev. 5 — 1 February 2011
25 pF load
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
[1][2]
[4]
[4]
[4]
Min
6
6
12.5
-
0
10
5
20
0
10
-
-
5
10
0
10
5
5
-
-
-
-
-
8T
-
10
1
RCLK
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
SC16C850L
© NXP B.V. 2011. All rights reserved.
Max
-
-
-
80
-
-
-
40
20
-
-
-
-
-
-
50
50
1T
1T
24T
50
(2
-
-
-
50
-
16
RCLK
RCLK
RCLK
 1)
39 of 55
Unit
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
ns
ns