SC28L92A1A,518 NXP Semiconductors, SC28L92A1A,518 Datasheet - Page 40

IC UART DUAL W/FIFO 44-PLCC

SC28L92A1A,518

Manufacturer Part Number
SC28L92A1A,518
Description
IC UART DUAL W/FIFO 44-PLCC
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet

Specifications of SC28L92A1A,518

Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935263293518
SC28L92A1A-T
SC28L92A1A-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC28L92A1A,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC28L92_7
Product data sheet
Table 45.
Bit
3 and 2
1 and 0
Symbol
-
-
OPCR - Output configuration control register (address 0xD) bit description
Description
OP3 output select
OP2 output select
Rev. 07 — 19 December 2007
00 = The complement of OPR[3]
01 = The counter/timer output, in which case OP3 acts as an open-drain
output. In the timer mode, this output is a square wave at the programmed
frequency. In the counter mode, the output remains HIGH until terminal
count is reached, at which time it goes LOW. The output returns to the
HIGH state when the counter is stopped by a stop counter command. Note
that this output is not masked by the contents of the IMR.
10 = The 1 clock for the channel B transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free running
1 clock is output.
11 = The 1 clock for the channel B receiver, which is the clock that
samples the received data. If data is not being received, a free running 1
clock is output.
00 = The complement of OPR[2]
01 = The 16 clock for the channel A transmitter. This is the clock selected
by CSRA[3:0], and will be a 1 clock if CSRA[3:0] = 1111.
10 = The 1 clock for the channel A transmitter, which is the clock that
shifts the transmitted data. If data is not being transmitted, a free running
1 clock is output.
11 = The 1 clock for the channel A receiver, which is the clock that
samples the received data. If data is not being received, a free running 1
clock is output.
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
SC28L92
© NXP B.V. 2007. All rights reserved.
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