LMH6521SQ/NOPB National Semiconductor, LMH6521SQ/NOPB Datasheet - Page 17

• Manufacturer Part Number: LMH6521SQ/NOPB
• Manufacturer: National Semiconductor

Specifications of LMH6521SQ/NOPB

• Lead Free Status / Rohs Status: Compliant

PULSE MODE (MOD1= 0, MOD0 = 1)
Pulse mode is a simple yet fast way to adjust gain settings.
Using only two control lines per channel the LMH6521 gain
can be changed by simple up and down signals. Gain steps
are selectable either by hard wiring the board or using two
additional logic inputs. For a system where gain changes can
be stepped sequentially from one gain to the next and where
board space is limited this mode may be the best choice. The
ENA and ENB pins are fully active during pulse mode, and
the channel gain state is preserved during the disabled state.
Refer to
initions of the LMH6521 in pulse mode.
In this mode the gain step size can be selected from a choice
of 0.5, 1, 2 or 6dB steps. During operation the gain can be
quickly adjusted either up or down one step at a time by a
negative pulse on the UP or DN pins. As shown in
each gain step pulse must have a logic high state of at least
t
pulse to register as a gain change signal.
To provide a known gain state there is a reset feature in pulse
mode. To reset the gain to maximum gain both the UP and
DN pins must be strobed low together as shown in
15. There must be an overlap of at least t
reset to register.
THERMAL MANAGEMENT
The LMH6521 is packaged in a thermally enhanced LLP
package and features an exposed pad that is connected to
the GND pins. It is recommended that the exposed pad be
attached directly to a large power supply ground plane for
maximum heat dissipation. The thermal advantage of the LLP
package is fully realized only when the exposed die attach
pad is soldered down to a thermal land on the PCB board with
the through vias planted underneath the thermal land. The
thermal land can be connected to any ground plane within the
Parameter
t
t
t
t
PW
PL
PH
SU
H
= 20 ns and a logic low state of at least t
Digital Control Mode Pin Functions
FIGURE 15. Pulse Mode Timing
FIGURE 14.
Description
Minimum clock low time (clock duty dycle)
Minimum clock high time (clock duty cycle)
Input data setup time
Input data hold time
RW
PG
table for pin def-
= 20 ns for the
= 20 ns for the
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Figure 15
Data Input on SDI Pin
Figure
Write Timing
17
PCB. However, it is also very important to maintain good high
speed layout practices when designing a system board.
The LMH6521EVAL evaluation board implemented an eight
metal layer design with (a) 4 oz. copper inner ground planes
(b) additonal through vias and (c) maximum bottom layer met-
al coverage to assist with device heat dissipation. Please refer
to the LMH6521EVAL evaluation board application note 2045
for suggested layout techniques.
Package information is available on the National web site.
http://www.national.com/packaging/folders/SQA32A.html
INTERFACE TO ADC
The LMH6521 was designed to be used with National
Semiconductor's high speed ADC's. As shown in
coupling provides the best flexibility especially for IF sub-
sampling applications. For DC coupled applications the use
of a level shifting amplifier or a resistive biasing network may
be possible.
The inputs of the LMH6521 will self bias to the optimum volt-
age for normal operation. The internal bias voltage for the
inputs is approximately mid rail which is 2.5V with the typical
5V power supply condition. In most applications the LMH6521
input will need to be AC coupled.
The LMH6521 output common mode voltage is biased to 0V
and has a maximum differential output voltage swing of
10V
most ADCs AC coupling is required. Since most often a band
pass filter is desired between the amplifier and ADC the band-
pass filter can be configured to block the DC voltage of the
amplifier output from the ADC input.
ple bandpass filter configuration that could be designed for a
200Ω impedance system.
FIGURE 16. Output Voltage with Respect to Output
PPD
as shown in
Figure
Common Mode
16. This means that for driving
Figure 17
shows a sam-
Figure
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1, AC