LMH6521SQ/NOPB National Semiconductor, LMH6521SQ/NOPB Datasheet - Page 14

• Manufacturer Part Number: LMH6521SQ/NOPB
• Manufacturer: National Semiconductor

Specifications of LMH6521SQ/NOPB

• Lead Free Status / Rohs Status: Compliant

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PARALLEL MODE (MOD1= 1, MOD0 = 1)
When designing a system that requires very fast gain
changes parallel mode is the best selection. Refer to
Control Mode Pin Functions
LMH6521 in parallel mode.
The LMH6521 has a 6-bit gain control bus as well as latch
pins LATA and LATB for channels A and B. When the latch
pin is low, data from the gain control pins is immediately sent
to the gain circuit (i.e. gain is changed immediately). When
the latch pin transitions high the current gain state is held and
subsequent changes to the gain set pins are ignored. To min-
imize gain change glitches multiple gain control pins should
not change while the latch pin is low. Gain glitches could result
from timing skew between the gain set bits. This is especially
the case when a small gain change requires a change in state
of three or more gain control pins. If continuous gain control
is desired the latch pin can be tied to ground. This state is
called transparent mode and the gain pins are always active.
In this state the timing of the gain pin logic transitions should
be planned carefully to avoid undesirable transients
ENA and ENB pins are provided to reduce power consump-
tion by disabling the highest power portions of the LMH6521.
The gain register will preserve the last active gain setting dur-
ing the disabled state. These pins will float high and can be
left disconnected if they won't be used. If the pins are left dis-
connected a 0.01uF capacitor to ground will help prevent
external noise from coupling into these pins.
Figure
in parallel mode with respect to the latch pin.
FIGURE 8. Parallel Mode Connection Not Using Latch
FIGURE 7. Parallel Mode Connection for Fastest
7,
Figure
Pins (Latch pins tied to logic low state)
8, and
Figure 9
Response
table for pin definitions of the
show the various connections
30120117
30120118
Digital
14
FIGURE 9. Parallel Mode Connection Using Latch Pins to
SERIAL MODE — SPI ™ COMPATIBLE INTERFACE
(MOD1= 1, MOD0 = 0)
Serial interface allows a great deal of flexibility in gain pro-
gramming and reduced board complexity. Using only 4 wires
for both channels allows for significant board space savings.
The trade off for this reduced board complexity is slower re-
sponse time in gain state changes. For systems where gain
is changed only infrequently or where only slow gain changes
are required serial mode is the best choice. Refer to
Control Mode Pin Functions
LMH6521 in serial mode.
The LMH6521 has a serial interface that allows access to the
control registers. The serial interface is a generic 4-wire syn-
chronous interface that is compatible with SPI standard inter-
faces and used on many microcontrollers and DSP con-
trollers.
The serial mode is active when the two mode pins are set as
follows: MOD1=1, MOD0=0). In this configuration the pins
function as shown in the pin description table. The SPI inter-
face uses the following signals: clock input (CLK), serial data
in (SDI), serial data out, and serial chip select (CS)
ENA and ENB pins are active in serial mode. For fast disable
capability these pins can be used and the serial register will
hold the last active gain state. These pins will float high and
can be left disconnected for serial mode. The serial control
bus can also disable the DVGA channels, but at a much slow-
er speed. The serial enable function is an AND function. For
a channel to be active both the enable pin and the serial con-
trol register must be in the enabled state. To disable a channel
either method will suffice. See the Typical Performance sec-
tion for disable and enable timing information.
LATA and LATB pins are not active during serial mode.
The serial clock pin CLK is used to register the input data that
is presented on the SDI pin on the rising edge; and to source
the output data on the SDO pin on the falling edge. User may
disable clock and hold it in the low state, as long as the clock
pulse-width minimum specification is not violated when the
clock is enabled or disabled.
The chip select pin CS starts a new register access with each
assertion - i.e., the SDATA field protocol is required. The user
is required to deassert this signal after the 16th clock. If the
SCSb is deasserted before the 16th clock, no address or data
write will occur. The rising edge captures the address just
shifted-in and, in the case of a write operation, writes the ad-
dressed register. There is a minimum pulse-width require-
ment for the deasserted pulse - which is specified in the
Electrical Specifications section.
SDI is an input pin for the serial data. It must observe setup/
hold requirements with respect to the SCLK. Each cycle is 16-
bits long
Mulitplex Digital Data
table for pin definitions of the
30120119
Digital