SC16C752BIBS,128 NXP Semiconductors, SC16C752BIBS,128 Datasheet - Page 21

• Manufacturer Part Number: SC16C752BIBS,128
• Description: IC DUAL UART 64BYTE 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C752BIBS,128

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276389128; SC16C752BIBS-F; SC16C752BIBS-F

NXP Semiconductors
SC16C752B
Product data sheet
7.1 Receiver Holding Register (RHR)
7.2 Transmit Holding Register (THR)
Remark: Refer to the notes under
The receiver section consists of the Receiver Holding Register (RHR) and the Receiver
Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data
from the RX terminal. The data is converted to parallel data and moved to the RHR. The
receiver section is controlled by the Line Control Register. If the FIFO is disabled, location
zero of the FIFO is used to store the characters.
Remark: In this case, characters are overwritten if overflow occurs.
If overflow occurs, characters are lost. The RHR also stores the error status bits
associated with each character.
The transmitter section consists of the Transmit Holding Register (THR) and the Transmit
Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and
shifts it into the TSR, where it is converted to serial data and moved out on the TXn
terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are
lost if overflow occurs.
All information provided in this document is subject to legal disclaimers.
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 6 — 30 November 2010
Table 9
for more register access information.
SC16C752B
© NXP B.V. 2010. All rights reserved.
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