SC16IS752IPW,112 NXP Semiconductors, SC16IS752IPW,112 Datasheet - Page 40

• Manufacturer Part Number: SC16IS752IPW,112
• Description: IC UART DUAL 12C/SPI 28TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS- 232 or RS- 485r

Specifications of SC16IS752IPW,112

• Number Of Channels: 2, DUART
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Features: Low Current
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 95 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4016-5; 935279292112; SC16IS752IPW; SC16IS752IPW

NXP Semiconductors
SC16IS752_SC16IS762_7
Product data sheet
Fig 18. Master writes to slave
Fig 19. Master read from slave
(1) See
(1) See
S
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
White block: host to SC16IS752/SC16IS762
Grey block: SC16IS752/SC16IS762 to host
SLAVE ADDRESS
Table 33
Table 33
S
for additional information.
for additional information.
SLAVE ADDRESS
The register read cycle (see
sending a slave address with the direction bit set to WRITE with a following subaddress.
Then, in order to reverse the direction of the transfer, the master issues a Repeated
START followed again by the device address, but this time with the direction bit set to
READ. The data bytes starting at the internal subaddress will be clocked out of the device,
each followed by a master-generated acknowledge. The last byte of the read cycle will be
followed by a negative acknowledge, signalling the end of transfer. The cycle is terminated
by a STOP signal.
Table 33.
Bit
7
6:3
2:1
0
W
Register address byte (I
Name
-
A[3:0]
CH1, CH0
-
A
W
REGISTER ADDRESS
Dual UART with I
A
Rev. 07 — 19 May 2008
REGISTER ADDRESS
Figure
Function
not used
UART’s internal register select
Channel select.
not used
00 = channel A
01 = channel B
10 = reserved
11 = reserved
2
(1)
C)
19) commences in a similar manner, with the master
A
2
SC16IS752/SC16IS762
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
nDATA
(1)
S
A
SLAVE ADDRESS
A
nDATA
LAST DATA
A
002aab047
R
© NXP B.V. 2008. All rights reserved.
P
NA
A
002aab048
P
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