SC16C850IBS,151 NXP Semiconductors, SC16C850IBS,151 Datasheet - Page 28

IC UART SGL-CH 3.3V 32-HVQFN

SC16C850IBS,151

Manufacturer Part Number
SC16C850IBS,151
Description
IC UART SGL-CH 3.3V 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C850IBS,151

Package / Case
32-VFQFN Exposed Pad
Features
Programmable
Number Of Channels
1, UART
Fifo's
128 Byte
Protocol
RS485
Voltage - Supply
2.5 V ~ 3.3 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.5 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4778
935283103151
NXP Semiconductors
SC16C850
Product data sheet
7.6 Modem Control Register (MCR)
Table 18.
This register controls the interface with the modem or a peripheral device.
Table 19.
LCR[1]
0
0
1
1
Bit
7
6
5
4
3
2
1
0
Symbol
MCR[7]
MCR[6]
MCR[5]
MCR[4]
MCR[3]
MCR[2]
MCR[1]
MCR[0]
LCR[1:0] word length
Modem Control Register bits description
LCR[0]
0
1
0
1
All information provided in this document is subject to legal disclaimers.
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
Description
Clock select
IR enable (see
Interrupt type (Intel mode only). In Intel mode (16/68 = 1), this pin
determines the interrupt output pin configuration.
In Motorola mode (16/68 = 0), the output is always open-drain.
Loopback. Enable the local loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI
are disconnected from the SC16C850 I/O pins. Internally the modem data
and control pins are connected into a loopback data configuration (see
Figure
operational. The Modem Control Interrupts are also operational, but the
interrupts’ sources are switched to the lower four bits of the Modem Control.
Interrupts continue to be controlled by the IER register.
OP2. This bit is used for internal Loopback mode only. In Loopback mode,
this bit is used to write the state of the modem CD interface signal.
OP1. This bit is used for internal Loopback mode only. In Loopback mode,
this bit is used to write the state of the modem RI interface signal.
RTS
DTR
Rev. 2 — 11 November 2010
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While
in this mode, the TX/RX output/inputs are routed to the infrared
encoder/decoder. The data input and output levels will conform to the
IrDA infrared interface requirement. As such, while in this mode, the
infrared TX output will be a logic 0 during idle data conditions.
logic 0 = CMOS output
logic 1 = open-source. A 300 Ω to 500 Ω pull-down resistor is required.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
9). In this mode, the receiver and transmitter interrupts remain fully
Word length (bits)
5
6
7
8
Figure
22).
SC16C850
© NXP B.V. 2010. All rights reserved.
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