PEF 82912 F V1.4 Infineon Technologies, PEF 82912 F V1.4 Datasheet - Page 21

• Manufacturer Part Number: PEF 82912 F V1.4
• Description: IC MODULAR ISDN NT INTELL TQFP64
• Manufacturer: Infineon Technologies
• Series: Q-SMINT®r

Specifications of PEF 82912 F V1.4

• Function: Second Generation Modular
• Interface: ISDN
• Mounting Type: Surface Mount
• Package / Case: 64-LFTQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Voltage - Supply: -
• Power (watts): -
• Operating Temperature: -
• Number Of Circuits: -
• Other names: PEF82912FV1.4XT; PEF82912FV14XP; SP000007558; SP000007559

2
2.1
External Reset Input
At the RST input an external reset can be applied forcing the Q-SMINT
state. This external reset signal is additionally fed to the RSTO output.
Reset Ouput
If VDDDET is active, then the deactivation of a reset output on RSTO is delayed by
t
Reset Generation
The Q-SMINT
and Under Voltage Detection (UVD) circuit (see
external components.
The POR/UVD circuit can be disabled via pin VDDDET.
The requirements on V
Chapter
Clocks and Data Lines During Reset
During reset the data clock (DCL) and the frame synchronization (FSC) keep running.
During reset DD and DU are high; with the exception of:
• The output C/I code from the U-Transceiver on DD is ’DR’ = 0000
• The output C/I code from the S-Transceiver on DU is ’TIM’ = 0000.
Data Sheet
DEACT
(see
4.6.3.
Functional Description
Reset Generation
Table

O has an on-chip reset generator based on a Power-On Reset (POR)
22).
DD
ramp-up during power-on reset are described in
13
Table
22). The POR/UVD requires no
Functional Description
PEF 80912/80913

O in the reset
2001-03-29