595CG160M000DG Silicon Laboratories Inc, 595CG160M000DG Datasheet

595CG160M000DG

Manufacturer Part Number

595CG160M000DG

Description

Manufacturer

Silicon Laboratories Inc

Datasheet

1.595CG160M000DG.pdf (12 pages)

Specifications of 595CG160M000DG

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Features



Applications



Description

The Si595 VCXO utilizes Silicon Laboratories’ advanced DSPLL

provide a low-jitter clock at high frequencies. The Si595 is available with

any-rate output frequency from 10 to 525 MHz. Unlike traditional VCXOs,

where a different crystal is required for each output frequency, the Si595

uses one fixed crystal to provide a wide range of output frequencies. This IC-

based approach allows the crystal resonator to provide exceptional

frequency stability and reliability. In addition, DSPLL clock synthesis

provides supply noise rejection, simplifying the task of generating low-jitter

clocks in noisy environments. The Si595 IC-based VCXO is factory-

configurable for a wide variety of user specifications including frequency,

supply voltage, output format, tuning slope, and absolute pull range (APR).

Specific configurations are factory programmed at time of shipment, thereby

eliminating the long lead times associated with custom oscillators.

Functional Block Diagram

Preliminary Rev. 0.2 8/09

O L TAG E

Available with any-rate output

frequencies from 10 to 525 MHz

3rd generation DSPLL

superior jitter performance

Internal fixed fundamental mode

crystal frequency ensures high

reliability and low aging

SONET/SDH (OC-3/12/48)

Networking

SD/HD SDI/3G SDI video

525 MH

- C

Frequency

Fixed

ONTR OLLED

ADC

with

Clock Synthesis



10–525 MHz

Any-rate

DSPLL

FTTx

Clock recovery and jitter cleanup PLLs

FPGA/ASIC clock generation



Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

–40 to +85 ºC operating range

CLK–

GND

RYSTAL

CLK+

circuitry to

S C I L L A T O R

GND

Ordering Information:

Pin Assignments:

See page 7.

See page 6.

Si5602

(Top View)

(VCXO)

Si595

E V I S I O N

CLK–

CLK+

Si595

Related parts for 595CG160M000DG

595CG160M000DG Summary of contents

Page 1

TAG E ONTR OLLED 10 525 Features  Available with any-rate output frequencies from 10 to 525 MHz ®  3rd generation DSPLL with superior jitter performance  Internal fixed fundamental mode ...

Si 595 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter 1 Supply Voltage Supply Current 2 Output Enable (OE) Operating Temperature Range Notes: 1. Selectable parameter specified by part number. See 3. "Ordering Information" on page 7 for further ...

Page 3

Table 3. CLK± Output Frequency Characteristics Parameter Symbol 1,2,3 f Nominal Frequency O 1,4 Temperature Stability 1,4 Absolute Pull Range APR 5 Power up Time t OSC Notes: 1. See Section 3. "Ordering Information" on page 7 for further details. ...

Page 4

Si 595 Table 5. CLK± Output Phase Jitter Parameter Symbol 1,2 Phase Jitter (RMS) for MHz < F OUT OUT 525 MHz Notes: 1. Differential Modes: LVPECL/LVDS/CML. Refer to AN256 and AN266 for further information. 2. For ...

Page 5

Table 8. Absolute Maximum Ratings Parameter Input Voltage Storage Temperature ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile) Soldering Temperature Time @ T PEAK Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to ...

Page 6

Si 595 2. Pin Descriptions Pin Name OE* 3 GND 4 CLK+ CLK– 5 (N/C for CMOS *Note: OE pin includes a 17 k resistor to V See 3. "Ordering Information" on page ...

Page 7

Ordering Information The Si595 supports a variety of options including frequency, temperature stability, tuning slope, output format, and V . Specific device configurations are programmed into the Si595 at time of shipment. Configurations are DD specified using the Part ...

Page 8

Si 595 4. Outline Diagram and Suggested Pad Layout Figure 2 illustrates the package details for the Si595. Table 11 lists the values for the dimensions shown in the illustration. Table 11. Package Diagram Dimensions (mm) Dimension ...

Page 9

Si5xx Mark Specification Figure 3 illustrates the mark specification for the Si595. Table 12 lists the line information. Table 12. Si5xx Top Mark Description Line Position 1 1–10 “SiLabs”+ Part Family Number, 595 (First 3 characters in part number) ...

Page 10

Si 595 6. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si595. Table 13 lists the values for the dimensions shown in the illustration. Table 13. PCB Land Pattern Dimensions (mm) Dimension D2 e ...

Page 11

OCUMENT HANGE IST Revision 0.1 to Revision 0.2  Updated Table 5, “CLK± Output Phase Jitter,” on page 4. Updated typical phase jitter from 0.6 to 0.7 ps for  380 ppm/V. : Preliminary Rev. ...

Page 12

... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...

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