571AMC000154DG Silicon Laboratories Inc, 571AMC000154DG Datasheet - Page 16

• Manufacturer Part Number: 571AMC000154DG
• Manufacturer: Silicon Laboratories Inc

Specifications of 571AMC000154DG

• Lead Free Status / Rohs Status: Compliant

Si570/Si571
3.2. I
The control interface to the Si570 is an I
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup.Fast mode
operation is supported for transfer rates up to 400 kbps
as specified in the I
16
S Slave Address
S Slave Address
(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
S – START condition
P – STOP condition
2
Required after the last data byte to signal the end of the read comand to the slave.
C Interface
From master to slave
2
C-Bus Specification standard.
0
0
(Optional 2
A
A
Byte Address
Byte Address
Figure 5. I
nd
2
C-compatible
data byte and acknowledge illustrated)
Read Command
Write Command
A
A
From slave to master
2
C Command Format
S
Rev. 1.2
Data
Slave Address 1
Figure 5 shows the command format for both read and
write access. Data is always sent MSB. Data length is 1
byte. Read and write commands support 1 or more data
bytes as illustrated. The master must send a Not
Acknowledge and a Stop after the last read data byte to
terminate the read command. The timing specifications
and timing diagram for the I2C bus can be found in the
I2C-Bus Specification standard (fast mode operation).
The device I2C address is specified in the part number.
A
Data
A
A
P
Data
A
Data
N
P