PEB 3081 H V1.4 Infineon Technologies, PEB 3081 H V1.4 Datasheet
PEB 3081 H V1.4
Specifications of PEB 3081 H V1.4
PEB3081HV14XP
SP000007583
SP000007584
Related parts for PEB 3081 H V1.4
PEB 3081 H V1.4 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Data Sheet Revision History: Previous Version: Page Subjects (major changes since last revision) Chapter 1 Comparison SBCX/SBCX-X Chapter S- Transceiver Synchronization New 3.3.6.2 Chapter Test Functions extended 3.3.10 Chapter CDA Handler Description extended 3.7.1.1 Chapter TIC Bus Access Control: Note ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.5.2.4 Infos on S/T (LT- ...
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Table of Contents 4.1.10 TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . . 134 4.1.11 SQRR1 - S/Q-Channel Receive Register ...
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Table of Contents 4.4.4 AUXM - Auxiliary Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 4.4.5 ...
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List of Figures Figure 1 Logic Symbol of the SBCX ...
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List of Figures Figure 39 Example of Activation/Deactivation initiated by the Terminal (TE). Activation/Deactivation completely under Software Control . . . . . . . . 77 Figure 40 Example of Activation/Deactivation initiated by the Network Termination (NT). Activation/Deactivation completely ...
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List of Tables Table 1 Comparison of the SBCX-X with the Previous Version SBCX . . . . . . . 11 Table 2 SBCX-X Pin Definitions and Functions . . . . . . . . . . . ...
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Overview The S/T Bus Interface Circuit Extended (SBCX-X) implements the four-wire S/T interface used to link voice/data ISDN terminals, network terminators and PBX trunk lines to a central office based on the SBCX PEB 2081, and provides ...
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Table 1 Comparison of the SBCX-X with the Previous Version SBCX (cont’d) Controller data access to IOM-2 timeslots Data control and manipulation Auxiliary Interface IOM channel select (LT modes) LED pin Output pin for D-channel active indication Control input pin ...
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Table 1 Comparison of the SBCX-X with the Previous Version SBCX (cont’d) Layer 1 state machine Layer 1 state machine in software Reset Signals Reset Sources Interrupt Output Signals Pin SCLK Data Sheet SBCX-X PEB 3081 With changes for correspondence ...
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S/T Bus Interface Circuit Extended SBCX-X Version 1.4 1.1 Features • Full duplex S/T interface transceiver according to ITU-T I.430 • Successor of SBCX PEB 2081 in 3.3 V technology • Conversion of the frame structure between ...
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Power supply 3.3 V • 3.3 V output drivers, inputs are 5 V safe • Advanced CMOS technology 1.2 Logic Symbol The logic symbol gives an overview of the SBCX-X functions. It must be noted that not all functions ...
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Typical Applications The SBCX-X is designed for the user area of the ISDN basic access. By programming the corresponding operating mode it may be used at both ends of these interfaces. Figure 2 illustrates the general application fields of ...
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Pin Configuration BCL / SCLK DU DD FSC DCL VSS VSS VDD MODE0 MODE1 / EAW ACL Figure 3 Pin Configuration of the SBCX-X (P-MQFP-44) Data Sheet P-MQFP- ...
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BCL / SCLK DU DD FSC DCL VSS VSS VDD MODE0 MODE1 / EAW ACL n.c. Figure 4 Pin Configuration of the SBCX-X (P-TQFP-48) Data Sheet P-TQFP- ...
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Table 2 SBCX-X Pin Definitions and Functions Pin No. Symbol MQFP- TQFP Host Interface 9 10 SCL 10 11 SDR 11 12 SDX INT 5 5 RES IOM-2 Interface 37 40 FSC 38 ...
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Table 2 SBCX-X Pin Definitions and Functions (cont’d) Pin No. Symbol MQFP- TQFP BCL/ SCLK SDS1 18 20 SDS2 Miscellaneous 28 31 SX1 29 32 SX2 32 35 ...
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Table 2 SBCX-X Pin Definitions and Functions (cont’d) Pin No. Symbol MQFP- TQFP AUX0 21 23 AUX1 22 24 AUX2 42 45 MODE0 43 46 MODE1 EAW 6 6 RSTO 17 19 C768 14 16 DCA ...
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Table 2 SBCX-X Pin Definitions and Functions (cont’d) Pin No. Symbol MQFP- TQFP DCI 16 18 SGO 44 47 ACL 15, n.c. 30, 48 Power Supply V 8, 13, 23, ...
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Description of Functional Blocks 3.1 General Functions and Device Architecture Figure 5 shows the architecture of the SBCX-X containing the following functions: • S/T-interface transceiver supporting TE, LT-T, LT-S, NT and intelligent NT modes • Serial Control Interface (SCI) ...
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General Auxiliary Purpose Interface I/Os Figure 5 Functional Block Diagram of the SBCX-X Data Sheet Description of Functional Blocks Peripheral Devices IOM-2 Interface IOM-2 Handler MONITOR TIC C/I Handler Serial Host Interface Reset (SCI) Interrupt generation Host 24 SBCX-X PEB ...
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Microcontroller Interface The SBCX-X supports a serial micrcontroller interface. For applications where no controller is connected to the SBCX-X programming is done via the IOM-2 MONITOR channel from a master device. In such applications the SBCX-X operates in the ...
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Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the ...
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Programming Sequences The basic structure of a read/write access to the SBCX-X registers via the serial control interface is shown in Figure write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 7 Serial Control Interface Timing ...
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Header 40 : Non-interleaved A-D-A-D Sequences H The non-interleaved A-D-A-D sequence gives direct read/write access to the complete address range and can have any length. In this mode SDX and SDR can be connected together allowing data transmission on one ...
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Header 41 : Non-interleaved A-D-D-D Sequence H This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D read access. This mode is useful for reading status information before writing to the HDLC XFIFO. The termination condition of ...
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MASK ISTA ST ST CIC CIC AUX AUX TRAN TRAN MOS MOS Interrupt Figure 8 Interrupt Status and Mask Registers All five interrupt bits in the ISTA register point at interrupt sources in the Monitor handler (MOS), C/I handler (CIC), ...
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Reset Generation Figure 9 shows the organization of the reset generation of the device. . 125µs £ t £ 250µs C/I Code Change (Exchange Awake) 125µs £ t £ 250µs EAW (Subscriber Awake) 125µs £ t £ 250µs Watchdog ...
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Table 5 Reset Source Selection RSS2 RSS1 Bit 1 Bit • C/I Code Change (Exchange Awake) A change in the downstream C/I channel (C/I0) generates an external reset pulse of 125 ...
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BCL clock cycles. The address range of the registers which will be reset at each SRES bit is listed in 3.2.5 Timer Modes The SBCX-X provides one timer which can be used ...
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The host starts and stops the timer in TIMR.CNT is operating in count down mode, for TIMR.TMD=1 a periodic interrupt AUXI.TIN is generated. The timer length (for count down timer) or the timer period (for periodic timer), respectively, can be ...
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Activation Indication via Pin ACL The activated state of the S-interface is directly indicated via pin ACL (Activation LED). An LED with pre-resistance may directly be connected to this pin and a low level is driven on ACL as ...
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S/T-Interface The layer-1 functions for the S/T interface of the SBCX-X are: – line transceiver functions for the S/T interface according to the electrical specifications of ITU-T I.430; – conversion of the frame structure between IOM-2 and S/T interface; ...
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SBCX SBCX-X TR LT-T 1) The maximum line attenuation tolerated by the SBCX kHz. TR SBCX-X TE1 £ £ .... SBCX-X TE1 Figure 14 Wiring Configurations in User ...
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S/T-Interface Coding Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance information. Line Coding The following figure illustrates the line ...
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Figure 16 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N – ...
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S/T-Interface Multiframing According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel). The Q bits are defined to be the bits in ...
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TE Mode After multiframe synchronization has been established, the Q data will be inserted at the upstream (TE ® NT) F bit position in each 5th S/T frame (see A When synchronization is not achieved or lost, each received F ...
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Data Transfer and Delay between IOM-2 and S/T TE mode In the state F7 (Activated the internal layer-1 statemachine is disabled and XINF of register TR_CMD is programmed to ’011’ the B1, B2, D and E bits ...
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-> -> FSC Mapping of B-Channel Timeslots Mapping of a 4-bit group of D-bits on S and IOM depends ...
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-> -> FSC Figure 19 Data Delay between IOM-2 and S/T Interface with 8 IOM Channels (LT-S/NT mode only) E ...
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Transmitter Characteristics The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter which is realized as a symmetrical current limited voltage source ( mA). The equivalent circuit of the transmitter is shown in max The ...
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Receiver Characteristics The receiver consists of a differential input stage, a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators. A simplified equivalent circuit of the receiver is shown in ...
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S/T Interface Circuitry For both, receive and transmit direction a 1:1 transformer is used to connect the SBCX- X transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found in the chapter on electrical characteristics. The ...
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Protection Circuit for Transmitter SX1 SX2 Figure 24 External Circuitry for Transmitter Figure 24 illustrates the secondary protection circuit recommended for the transmitter. The external resistors ( .... are required in order to adjust the ...
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Between each receive line and the transformer resistor is used. This value is split into two resistors: one between transformer and protection diodes for current limiting during the 96 kHz test, and the second one between ...
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S/T Interface Delay Compensation (TE/LT-T Mode) The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog delay plus delay of the external circuitry) with respect to the received frame. To compensate additional delay introduced ...
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Figure 27 Disabling of S/T Transmitter 3.3.10 Test Functions The SBCX-X provides test and diagnostic functions for the S/T interface: Note: For more details please refer to the application note “Test Function of new S- Transceiver family” – The internal ...
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SX1 SX2 SCOUT-S(X) SR1 SR2 Figure 28 External Loop at the S/T-Interface – transmission of special test signals on the S/T interface according to the modified AMI code are initiated via a C/I command written in CIX0 register (see Two ...
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Clock Generation Figure 29 shows the clock system of the SBCX-X. The oscillator is used to generate a 7.68 MHz clock signal (f XTAL (8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames. ...
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Data Sheet Description of Functional Blocks 54 SBCX-X PEB 3081 2003-02-04 ...
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Note: The IOM-2 interface is adaptive. This means in LT-S/NT and LT-T mode other frequencies for BCL and DCL are possible in the range of 512-4096 kHz (DCL) and 256-2048 kHz (BCL). For details please refer to the application note ...
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Description of the Receive PLL (DPLL) The receive PLL performs phase tracking between the F/L transition of the receive signal and the recovered clock. Phase adjustment is done by adding or subtracting 0 XTAL period to or ...
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Oscillator Clock Output C768 The SBCX-X derives its system clocks from an external clock connected to XTAL1 (while XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and XTAL2. At pin C768 a buffered 7.68 ...
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Control of Layer-1 The layer-1 activation / deactivation can be controlled by an internal state machine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of ...
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State machines are the key to understanding the transceiver part of the SBCX-X. They include all information relevant to the user and enable him to understand and predict the behaviour of the SBCX-X. The state diagram notation is given in ...
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The state may be left by either of the following methods: – Leave for the state “F3 power up” in case C/I = “TIM” code is received. – Leave for state “F4 pending activation” in case C/I = AR8 or ...
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Pending Act. TIM RSY X TIM i4 F5 Unsynchronized i0*TO1 Synchronized Lost Framing ...
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SSP SCP SSP TMA SCP TIM DI Test Mode Figure 35 State Transition Diagram of Unconditional Transitions (TE, LT-T) 3.5.1.2 States (TE, LT-T) F3 Pending Deactivation State after deactivation from the S/T interface by INFO 0. ...
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F5 Unsynchronized Any signal except INFO detected on the S/T interface. F6 Synchronized The receiver has synchronized and detects INFO 2. INFO 3 is transmitted to synchronize the NT. F7 Activated The receiver has synchronized and detects ...
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C/I Codes (TE, LT-T) Command Activation Request with priority class 8 Activation Request with priority class 10 Activation Request Loop ARL Deactivation Indication Reset Timing Test mode SSP Test mode SCP Note: In the activated states (AI8, AI10 or ...
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Indication Deactivation Request Reset Test Mode Acknowledge Slip Detected Resynchronization during level detect Deactivation Request from F6 Power up Activation request Activation request loop ARL Illegal Code Violation Activation indication loop Activation indication with priority class 8 Activation indication with ...
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Infos on S/T (TE, LT-T) Receive Infos on S/T (Downstream) Name INFO 0 INFO 2 INFO 4 INFO X Transmit Infos on S/T (Upstream) Name INFO 0 INFO 1 INFO 3 Test INFO 1 Test INFO 2 Data Sheet ...
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State Machine LT-S Mode 3.5.2.1 State Transition Diagram (LT-S) RST TIM RES Reset i0 * RES DC Any State DC RSY ARD G2 Lost Framing S ARD = AR or ARL ...
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States (LT-S) G1 Deactivated The transceiver is not transmitting. There is no signal detected on the S/T interface, and no activation command is received in the C/I channel. The clocks are deactivated if MODE1.CFS is set to 1. Activation ...
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Test mode - SCP Continuous alternating pulses are sent on the S/T-interface. 3.5.2.3 C/I Codes (LT-S) Command Abbr. Deactivation DR Request Reset RES Send Single Pulses SSP Send Continuous SCP Pulses Activation Request AR Activation Request ARL Loop Deactivation DC ...
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Indication Abbr. Activation Indication AI Deactivation DI Indication 3.5.2.4 Infos on S/T (LT-S) Receive Infos on S/T (Downstream) I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 ...
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State Machine NT Mode 3.5.3.1 State Transition Diagram (NT) RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 ...
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Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’ itself , i.e. C/I-code ’SSP/SCP’ must not be followed by C/I-code ’SCP/SSP’ directly. 3.5.3.2 States (NT) G1 Deactivated The transceiver is not transmitting. There is ...
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G4 Pending Deactivation This state is triggered by a deactivation request DR, and is an unstable state. Indication DI (state “G4 wait for DR”) is issued by the transceiver when: either INFO 0 is received for a duration of 16 ...
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Command Abbr. Activation Indication AI Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code CVR Violation Activation Indication AI Deactivation DI Indication Data Sheet Description of Functional Blocks Code ...
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Command / Indicate Channel Codes (C/I0) - Overview The table below presents all defined C/I0 codes. A command needs to be applied continuously until the desired action has been initiated. Indications are strictly state orientated. Refer to the state ...
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Control Procedures 3.6.1 Example of Activation/Deactivation An example of an activation/deactivation of the S/T interface initiated by the terminal with the time relationships mentioned in the previous chapters is shown RSY Figure 38 ...
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Activation initiated by the Terminal INFO 1 has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is received. After ...
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Activation initiated by the Network Termination NT INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 3 has ...
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IOM-2 Interface The SBCX-X supports the IOM-2 interface in linecard mode and in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates ...
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IOM-2 Frame Structure (TE Mode) The frame structure on the IOM-2 data ports (DU, DD master device in IOM-2 terminal mode is shown in Ò Figure 41 IOM -2 Frame Structure in Terminal Mode The frame is composed ...
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IOM-2 Frame Structure (LT-S, LT-T Modes) This mode is used in LT-S and LT-T applications. The frame is a multiplex eight IOM-2 channels (DCL = 4096 kHz, see described above. The reset value for assignment to one ...
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IOM-2 Handler The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the SBCX-X and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all timeslots ...
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SDS2 SDS1 SCLK / BCL DCL FSC DD DU Figure 43 Architecture of the IOM Handler (Example Configuration) Data Sheet Description of Functional Blocks Data C/I0 B2, B1, D, Data C/I1 Data C/I0 Data Bus TIC Data Monitor Data ...
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Controller Data Access (CDA) With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the SBCX-X IOM-2 handler provides a very flexible solution for the host access IOM-2 time slots. The functional unit CDA ...
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TSa 1 0 Enable output input * (EN_O0) (EN_I0) CDAx0 1 0 TSa a,b = 0... the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and EN_I1, ...
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Looping Data TSa CDA10 TSa .TSS: .DPS ’0’ .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP c) Switching Data TSa CDA10 .TSS: TSa .DPS ’0’ .SWAP Figure 45 Examples for Data Access via CDAxy Registers a) ...
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Figure 46 shows the timing of looping TSa from 0...31) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD 0...31 FSC ...
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Shifting TSa ® TSb within one frame (a,b: 0...31 and b ³ a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa ® TSb in the next frame (a,b: 0...31 and ( <a) FSC DU TSa ...
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Monitoring Data Figure 48 gives an example for monitoring of two IOM-2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots with ...
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Synchronous Transfer While looping, shifting and switching the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). The microcontroller access to the CDAxy registers can be synchronized by means of ...
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Table 9 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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Figure 50 shows some examples based on the timeslot structure. Figure a) shows at which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure b) is identical to example 3 above, figure c) corresponds ...
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Restrictions Concerning Monitoring and Shifting Data Due to the hardware design, there are some restrictions for the CDA shifting data function and for the CDA monitoring data function. The selection of the CDA registers is restricted if other functional blocks ...
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Example: w CDA1_CR = 00 (inputs and outputs are disabled CDA10 = 5A (example CDA10 = FF (old value of previous programming CDA1_CR = 02 (output of CDA10 is enabled CDA10 = ...
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FSC DD, TS0 TS1 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 3: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 For all examples SDS_CONF.SDS1/2_BCL must be set to “0”. Figure ...
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Strobed IOM-2 Bit Clock The strobed IOM-2 bit clock is active during the programmed window. Outside the programmed window a ’0’ is driven. Two examples are shown in FSC DD, TS0 TS1 SDS1 (Example1) SDS1 (Example2) Setting ...
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IOM-2 Monitor Channel The IOM-2 MONITOR channel (see MONITOR channel between a master mode device and a slave mode device. The MONTIOR channel data can be controlled by the bits in the MONITOR control register (MON_CR). For the transmission ...
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As a slave device the transceiver part of the SBCX-X is programmed and controlled from a master device on IOM-2 (e.g. ISAR 34 PSB 7115). This is used in applications where no microcontroller is connected directly to the SBCX-X ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 54 MONITOR Channel Protocol (IOM-2) Before starting ...
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As a result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the transmitter. A new MONITOR data byte can now be written ...
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To control this handshake procedure a collision detection mechanism is implemented in the transmitter. This is done by making a collision check per bit on the transmitted MONITOR data and the MX bit. • Monitor data will be transmitted ...
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IOM -2 Frame No. MX (DU) MR (DD) Figure 55 Monitor Channel, Transmission Abort Requested by the Receiver IOM -2 Frame No. MR (DU) MX (DD) Figure 56 Monitor Channel, Transmission Abort Requested by the Transmitter IOM -2 Frame No. ...
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MONITOR Channel Programming as a Master Device As a master device the SBCX-X can program and control other devices attached to the IOM-2 interface. The master mode is selected by default if the serial control interface (SCI) is used ...
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DU 1st byte value DU 2nd byte value This identification sequence is usually done once, when the terminal is connected for the first time. This function is used so that the software can distinguish between different possible hardware configurations. However ...
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MONITOR Interrupt Logic Figure 58 shows the MONITOR interrupt structure of the SBCX-X. The MONITOR Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of ...
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C/I Channel Handling The Command/Indication channel carries real-time status information between the SBCX-X and another device connected to the IOM-2 interface. • One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the C/I handler ...
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The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case the occurrence of a code change in CIR1 will ...
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TIC Bus D-Channel Access Control The TIC bus is imlemented to organize the access to the layer-1 functions provided in the SBCX-X (C/I-channel) and to the D-channel from external communication controllers (Figure 60). Note: The TIC ...
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In the case of an access request to the C/I channel, the SBCX-X checks the Bus Accessed-bit BAC (bit 5 of last octet of CH2 on DU, see free“, which is indicated by a logical ’1’. If the bus is ...
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S-Bus Priority Mechanism for D-Channel The S-bus access procedure specified in ITU I.430 was defined to organize D-channel access with multiple TEs connected to a single S-bus To implement collision detection the D (channel) and E (echo) bits are ...
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A TE may start transmission of a layer-2 frame first when a certain number of consecutive 1s has been received on the echo channel. This number is fixed priority class 1 and priority class ...
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S-Bus D-channel Access Control in the SBCX-X The above described priority mechanism is fully implemented in the SBCX-X. For this purpose the D-channel collision detection according to ITU I.430 must be enabled by setting TR_MODE2.DIM2-0 to ’0x1’. In this case ...
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The arbiter permanently counts the “1s” in the upstream D-channel on IOM-2. If the necessary number of “1s” is counted and an HDLC controller on IOM-2 requests upstream D-channel access (BAC bit is set to 0), the arbiter allows this ...
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NT D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources on IOM-2 nor any of the terminals connected to the S-bus transmit in the D-channel. The SBCX-X S-transceiver thus receives BAC = “1” ...
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Terminal Transmits D-Channel Data Upstream The initial state is identical to that described in the last paragraph. When one of the connected S-bus terminals needs to transmit in the D-channel, access is established according to the following procedure: • ...
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Activation/Deactivation of IOM-2 Interface The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and the data lines are ...
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DCL is activated such that its first rising edge occurs with the beginning of the bit following the C/I (C/I0) channel. After the clocks have been enabled this is indicated by the PU code in the C/I channel and, consequently, ...
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Asynchronous Awake (LT-S, NT, Int. NT mode) The transceiver is in power down mode (deactivated state) and MODE1.CFS=1 (TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect circuit will asynchronously pull the ...
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Table 15 IOM-2 Channel Selection CH2 CH1 For DCL = 1.536 MHz one of the IOM-2 channels can be selected, for ...
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Detailed Register Description The register mapping of the SBCX-X is shown in FFh 70h 60h 40h 22h 00h Figure 67 Register Mapping of the SBCX-X The register set ranging from 22 handler registers. Data Sheet Detailed Register Description Figure ...
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The address range from 40 timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver data (TR), Monitor data (MON), C/I data (CI) and controller access data (CDA), serial data strobe signal (SDS), IOM interface (IOM) ...
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Transceiver, C/I-Channel Handler, Auxiliary Interface NAME 7 6 TR_STA RINF TR_CMD XINF SQRR1 MSYN MFEN SQXR1 0 MFEN SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34 SQXR2 SQX21SQX22SQX23SQX24SQX31 SQX32SQX33 SQX34 SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54 SQXR3 SQX41SQX42SQX43SQX44SQX51 SQX52SQX53 SQX54 ISTATR 0 x MASKTR 1 1 TR_ 0 0 MODE ...
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IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 Controller Data Access Register (CH10) CDA11 Controller Data Access Register (CH11) CDA20 Controller Data Access Register (CH20) CDA21 Controller Data Access Register (CH21) ...
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IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name 7 6 TR_CR EN_ EN_ D B2R (CI_CS=0) TRC_CR 0 0 (CI_CS=1) DCI_CR DPS_ EN_ CI1 CI1 (CI_CS=0) DCIC_CR 0 0 (CI_CS=1) MON_CR DPS EN_ MON SDS1_CR ENS_ ENS_ ...
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MOR MOX MOSR MDR MER MDA MOCR MRE MRC MSTA 0 0 MCONF 0 0 Interrupt, General Configuration Registers NAME 7 6 ISTA 0 0 MASK 1 1 AUXI 0 0 AUXM 1 1 MODE1 0 0 MODE2 0 0 ...
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Transceiver and C/I Registers 4.1.1 TR_MODE2 - Transceiver Mode Register 2 Value after reset TR_ 0 0 MODE2 DIM2-0 ... Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD). The ...
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CIR0 - Command/Indication Receive 0 Value after reset CIR0 CODR0 CODR0 ... C/I Code 0 Receive Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive ...
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CIX0 - Command/Indication Transmit 0 Value after reset CIX0 CODX0 CODX0 ... C/I-Code 0 Transmit Code to be transmitted in the C/I-channel 0. The code is only transmitted if the TIC bus is occupied. If TIC ...
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CIX1 - Command/Indication Transmit 1 Value after reset CIX1 CODX1 ... C/I-Code 1 Transmit Bits 7-2 of C/I-channel 1 timeslot. CICW... C/I-Channel Width CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel ...
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EN_ICV ... Enable Illegal Code Violation 0: normal operation 1: ICV enabled. The receipt of at least one illegal code violation within one multiframe is indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames. L1SW ... Enable ...
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TR_CONF1 - Transceiver Configuration Register 1 Value after reset TR_ 0 RPLL_ CONF1 ADJ RPLL_ADJ ... Receive PLL Adjustment 0: DPLL tracking step is 0.5 XTAL period per S-frame 1: DPLL tracking step is 1 XTAL ...
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PDS ... Phase Deviation Select Defines the phase deviation of the S-transmitter. 0: The phase deviation is 2 S-bits minus 7 oscillator periods plus analog delay plus delay of the external circuitry. 1: The phase deviation is 2 S-bits minus ...
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TR_STA - Transceiver Status Register Value after reset TR_ RINF STA Important: This register is used only if the Layer 1 state machine of the SBCX-X is disabled (TR_CONF0.L1SW = 1) and implemented in software! With ...
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TR_CMD - Transceiver Command Register Value after reset TR_ XINF CMD Important: This register is only writable if the Layer 1 state machine of the SBCX-X is disabled (TR_CONF0.L1SW = 1)! With the SBCX-X layer 1 ...
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LP_A ... Loop Analog The setting of this bit corresponds to the C/I command ARL. 0: Analog loop is open 1: Analog loop is closed internally or externally according to the EXLP bit in the TR_CONF0 register For general information ...
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SQXR1- S/Q-Channel TX Register 1 Value after reset SQXR1 0 MFEN MFEN ... Multiframe Enable Used to enable or disable the multiframe structure (see 0: S/T multiframe is disabled 1: S/T multiframe is enabled Readback value ...
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SQXR2 - S/Q-Channel TX Register 2 Value after reset SQXR2 SQX21 SQX22 SQX23 SQX24 SQX31 SQX32 SQX33 SQX34 SQX21-24, SQX31-34... Transmitted S Bits (NT mode only) Transmitted S bits in frames and 17 ...
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ISTATR 0 x For all interrupts in the ISTATR register the following logical states are defined: 0: Interrupt is not acitvated 1: Interrupt is acitvated x ... Reserved Bits set to “1” in this bit position must be ignored. ...
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The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1). 4.1.19 TR_MODE - Transceiver Mode Register 1 Value after reset: 000000xx 7 TR_ 0 0 MODE For general information please refer also to DCH_INH ... D-Channel ...
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Auxiliary Interface Registers 4.2.1 ACFG1 - Auxiliary Configuration Register 1 Value after reset ACFG1 0 0 For general information please refer to OD2-0 ... Output Driver Select for AUX2 - AUX0 0: output is open drain ...
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AOE - Auxiliary Output Enable Register Value after reset AOE 1 1 For general information please refer to OE2-0 ... Output Enable for AUX2 - AUX0 0: Pin AUX2-0 is configured as output. The value of ...
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ATX - Auxiliary Interface Transmit Register Value after reset ATX 0 0 AT2-0 ... Auxiliary Transmit A ’0’ or ’1’ in AT2-0 will drive a low or a high level at pin AUX2-0 if the corresponding ...
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XXX_TSDPxy - Time Slot and Data Port Selection for CHxy 7 XXX_ DPS 0 TSDPxy Register Register Address CDA_TSDP10 44 H CDA_TSDP11 45 H CDA_TSDP20 46 H CDA_TSDP21 47 H TR_TSDP_BC1 4C H TR_TSDP_BC2 4D H This register determines ...
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CDAx_CR - Control Register Controller Data Access CH1x 7 CDAx_ Register CDA1_CR CDA2_CR For general information please refer to EN_TBM ... Enable TIC Bus Monitoring 0: The TIC bus monitoring is disabled 1: The TIC bus ...
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TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0) Value after reset TR_CR EN_ EN_ D B2R Read and write access to this register is only possible if IOM_CR.CI_CS = 0. EN_D ... Enable Transceiver D-Channel Data EN_B2R ...
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TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1) Value after reset TRC_CR 0 0 Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1. Read access to this register is possible only ...
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DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1) Value after reset DCIC_CR 0 0 Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1. Read access to this register is possible ...
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MON_CR - Control Register Monitor Data Value after reset MON_CR DPS EN_ MON For general information please refer to DPS ... Data Port Selection 0: The Monitor data is output on DD and input from DU ...
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SDSx_CR - Control Register Serial Data Strobe x Value after reset SDSx_CR ENS_ ENS_ TSS TSS+1 Register SDS1_CR SDS2_CR This register is used to select position and length of the strobe signals. The length can be ...
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IOM_CR - Control Register IOM Data Value after reset IOM_CR SPU DIS_ AW SPU ... Software Power Up 0: The DU line is normally used for transmitting data 1: Setting this bit to ’1’ will pull ...
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EN_BCL ... Enable Bit Clock BCL/SCLK 0: The BCL/SCLK clock is disabled 1: The BCL/SCLK clock is enabled. CLKM ... Clock Mode If the transceiver is disabled (DIS_TR = ’1’ NT, LT-S and Int. NT mode the DCL ...
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STI - Synchronous Transfer Interrupt Value after reset STI STOV STOV 21 20 For all interrupts in the STI register the following logical states are applied: 0: Interrupt is not activated 1: Interrupt is activated The ...
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ASTI - Acknowledge Synchronous Transfer Interrupt Value after reset ASTI 0 0 For general information please refer to ACKxy ... Acknowledge Synchronous Transfer Interrupt After an STIxy interrupt the microcontroller has to acknowledge the interrupt by ...
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SDS_CONF - Configuration Register for Serial Data Strobes Value after reset SDS_ 0 0 CONF For general information on SDS1/2_BCL please refer to DIOM_INV ... DU/DD on IOM Timeslot Inverted 0: DU/DD are active during SDS1 ...
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MCDA - Monitoring CDA Bits Value after reset MCDA MCDA21 Bit7 Bit6 MCDAxy ... Monitoring CDAxy Bits Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register. This can be used ...
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MOSR - MONITOR Interrupt Status Register Value after reset MOSR MDR MER MDR ... MONITOR channel Data Received MER ... MONITOR channel End of Reception MDA ... MONITOR channel Data Acknowledged The remote end has acknowledged ...
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MIE ... MONITOR Interrupt Enable MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0). MXC ... MX Bit Control Determines the value of the MX bit: 0: The MX bit is always ’1’. 1: The MX ...
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Interrupt and General Configuration 4.4.1 ISTA - Interrupt Status Register Value after reset ISTA 0 0 For all interrupts in the ISTA register following logical states are applied: 0: Interrupt is not acitvated 1: Interrupt is ...
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MASK - Mask Register Value after reset MASK 1 1 For the MASK register following logical states are applied: 0: Interrupt is enabled 1: Interrupt is disabled Each interrupt source in the ISTA register can selectively ...
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AUXM - Auxiliary Mask Register Value after reset AUXM 1 1 For the MASK register following logical states are applied: 0: Interrupt is enabled 1: Interrupt is disabled Each interrupt source in the AUXI register can ...
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CFS ... Configuration Select This bit determines clock relations and recovery on S/T and IOM interfaces. 0: The IOM interface clock and frame signals are always active, "Power Down" state included. The states "Power Down" and "Power Up" are thus ...
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If RSS = ’00’ no above listed reset source is selected and therefore no reset is generated at RSTO. • Watchdog Timer After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started. During ...
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ID - Identification Register Value after reset DESIGN ... Design Number The design number allows to identify different hardware designs of the SBCX-X by software Version 1.4 H (all other codes ...
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TIMR - Timer Register Value after reset TIMR TMD 0 TMD ... Timer Mode The timer can be used in two different modes of operation. 0: Count Down Timer. An interrupt is generated only once after ...
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Electrical Characteristics 5.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Input/output voltage on any pin with respect to ground Maximum voltage on any pin with respect to ground Note: Stresses above those listed here may cause ...
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DC Characteristics = 3.3 V ± 5 Parameter H-input level (except pins SR1/2) L-input level (except pins SR1/2) H-output level (except pin XTAL2, SX1/2) L-output level (except pin XTAL2, SX1/2) Input leakage ...
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Capacitances = 25 ° 3 grounded. Parameter Input Capacitance I/O Capacitance Output Capacitance against V SS Data Sheet ± SSA SS Symbol ...
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Oscillator Specification Recommended Oscillator Circuits Crystal Oscillator Mode Figure 68 Oscillator Circuits Parameter Frequency Frequency calibration tolerance Load capacitance Oscillator mode Note important to note that the load capacitance ...
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AC Characteristics = ° 3 Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing measurements are made at 2.0 V ...
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IOM-2 Interface Timing Data is transmitted with the rising edge of DCL and sampled with its falling edge. Below figure shows double clock mode timing (the length of a timeslot is 2 DCL cycles), however, the timing parameters are ...
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DCL (I) FSC (I) DU/DD (I) DU/DD (O) SDS (O) Figure 71 IOM-2 Timing (LT-S, LT-T, NT mode) Parameter IOM output data delay IOM input data setup IOM input data hold FSC strobe delay (see note) Strobe signal delay BCL ...
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Note: Min. value in synchronous state, max. value in non-synchronous state. This results in a phase shift of FSC when the S-Bus gets activated, this is the FSC signal is shifted by 135 ns. This applies only to TE mode. ...
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Serial Control Interface (SCI) Timing SCL t 6 SDR SDX Figure 73 SCI Interface Parameter SCI Interface SCL cycle time SCL high time SCL low time CS setup time CS hold time SDR setup time SDR ...
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Reset Parameter Symbol Length of active t RES low state RES Figure 74 Reset Signal RES Data Sheet Limit Values Unit min DCL clock cycles t RES 174 SBCX-X PEB 3081 Electrical Characteristics Test Conditions ...
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S-Transceiver Parameter = 3.3 V ± Absolute value of output pulse amplitude | VSX2 – VSX1 | Transmitter output current Transmitter output impedance (SX1,2) Receiver Input impedance (SR1,2) Data Sheet ...
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Recommended Transformer Specification Parameter Symbol Transformer ratio Main inductance L Leakage inductance L Capacitance between C primary and secondary side Copper resistance R Note: In TE/LT-T mode, at the pulse shape measurement with a load of 400 W (e.g. ...
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Line Overload Protection The maximum input current for the S-transceiver lines (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse. The desctruction limits are shown in Figure i [ ...
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EMC / ESD Aspects To improve performance with respect to EMC and ESD requirements it is recommended to provide additional capacitors in the middle tap of the transformers (see below). The values for C1 and C2 should be in ...
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Package Outlines P-MQFP-44 (Plastic Metric Quad Flat Package) 0.8 +0.15 0 Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side You can find all of the current packages, types of packing, ...
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P-TQFP-48 (Plastic Thin Quad Flat Package) You can find all of the current packages, types of packing, and others on the Infineon Internet Page “Products”: http://www.infineon.com/products. SMD = Surface Mounted Device Data Sheet 179 SBCX-X PEB 3081 Package Outlines GPP05612 ...
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Appendix Transceiver, C/I-Channel Handler, Auxiliary Interface NAME 7 6 TR_ 0 0 MODE2 CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 TR_ DIS_ BUS CONF0 TR TR_ 0 RPLL_ CONF1 ADJ TR_ DIS_ PDS CONF2 TX TR_STA RINF TR_CMD XINF SQRR1 ...
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Transceiver, C/I-Channel Handler, Auxiliary Interface NAME 7 6 ISTATR 0 x MASKTR 1 1 TR_ 0 0 MODE ACFG1 0 0 ACFG2 0 0 AOE 1 1 ARX - - ATX 0 0 IOM Handler (Timeslot , Data Port Selection, ...
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CDA_ DPS 0 TSDP21 TR_ DPS 0 TSDP_ BC1 TR_ DPS 0 TSDP_ BC2 CDA1_ CDA2_ IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name 7 6 TR_CR EN_ EN_ D B2R ...
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SDS2_CR ENS_ ENS_ TSS TSS+1 IOM_CR SPU DIS_ AW STI STOV STOV 21 20 ASTI 0 0 MSTI STOV STOV 21 20 SDS_ 0 0 CONF MCDA MCDA21 MOR MOX MOSR MDR MER MDA MOCR MRE MRC MSTA 0 0 ...
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Interrupt, General Configuration Registers NAME 7 6 MODE2 SRES RES_ 0 CI TIMR TMD 0 Data Sheet INT_ 0 POL DESIGN 0 RES_ 0 RES_ MON IOM CNT reserved ...
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Index A Absolute maximum ratings 165 AC characteristics 169 ACFG1 register 140 ACFG2 register 140 ACKxy bits 153 ACL bit 140 Activation 76 Activation indication - pin ACL 35 Activation LED 35 Activation/deactivation of IOM-2 interface 116 AOE register 141 ...
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Index EN_B2/1X bits 145 EN_BCL bit 150 EN_CI1 bit 146 EN_D bit 145 EN_I0 bit 144 EN_I1 bit 144 EN_ICV bit 129 EN_MON bit 148 EN_O0 bit 144 EN_O1 bit 144 EN_SFSC bit 131 EN_TBM bit 144 ENS_TSSx bits 149 ...
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Index Monitoring TIC bus 89 MOR register 155 MOS bit 158 MOSR register 156 MOX register 155 MRC bit 156 MRE bit 156 MSTA register 157 MSTI register 153 MSYN bit 135 Multiframing 40 MXC bit 156 O OD2-0 bits ...
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Index LT-S mode 67 NT mode 71 TE and LT-T mode 60 STI register 152 STIxy bits 152, 153 Stop/Go bit 114, 127 STOVxy bits 152, 153 Strobed data clock 94 Subscriber awake 32 SWAP bit 144 Synchronous transfer 90 ...
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