PEB 20571 F V3.1 Infineon Technologies, PEB 20571 F V3.1 Datasheet - Page 256
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PEB 20571 F V3.1
Manufacturer Part Number
PEB 20571 F V3.1
Description
IC LINE CARD CTRLR DSP TQFP-100
Manufacturer
Infineon Technologies
Datasheet
1.PEB_20570_F_V3.1.pdf
(308 pages)
Specifications of PEB 20571 F V3.1
Function
PBX Controller with DSP
Interface
ISDN
Voltage - Supply
3.13 V ~ 3.47 V
Current - Supply
272.6mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Layer-1 Control, Signaling Control, Signal Processing, Voice Channel Handling
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Number Of Circuits
-
Other names
PEB20571FV3.1X
PEB20571FV31XP
SP000007539
PEB20571FV31XP
SP000007539
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6.2.11.8 FSC Control Register
FSC Control Register (2)
Reset value: 0002
Note: ’x’ = unused bits, read as 0
.
FSCEN
FSCSH
EFSCD
IFSCD
Data Sheet
15
7
x
x
FSC Clock Enable
0 =
1 =
Short FSC Pulse
0 =
1 =
External FSC Delay
0 =
1 =
Internal FSC Delay (only valid if CSTRAP: bit0 = 1)
0 =
1 =
H
14
6
x
x
FSC is disabled (stuck at '0')
FSC is enabled (default)
The next FSC pulse will be longer than 2 DCL cycles (default)
The next FSC pulse will be shorter than 2 DCL cycles (short FSC)
no delay between FSC and DCL rising edge (recommended for
VIP V2.1 and higher)
FSC rising edge is delayed by one CLK61 clock (16 ns) relative to
DCL/ DCL2000 (suitable only for VIP up to V1.1)
no delay between FSC and DCL rising edge (default)
FSC rising edge is delayed by one CLK61 clock (16 ns) relative to
DCL/ DCL2000 (only for test purpose)
Note: If only one short FSC pulse is needed, this bit should be reset
to '0' by the DELIC software, after the next FSC rising edge
detection (after the beginning of the next frame). It is not
executed automatically by the hardware.
13
5
x
x
12
4
read/write
x
x
239
IFSCD
11
3
x
EFSCD
10
2
x
Register Description
FSCEN
Address: D087
9
x
1
PEB 20570
PEB 20571
2003-07-31
FSCSH
8
0
x
H
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