PEB2245N-V12 Infineon Technologies, PEB2245N-V12 Datasheet - Page 31

• Manufacturer Part Number: PEB2245N-V12
• Description: IC SWITCHING/CONFER MULTI 44PLCC
• Manufacturer: Infineon Technologies
• Series: MUSAC™r

Specifications of PEB2245N-V12

• Function: Multipoint Switching and Conferencing
• Interface: PCM
• Voltage - Supply: 5V
• Current - Supply: 12mA
• Power (watts): 100mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Includes: Clock Shift, Space Switch Mode, Time and Space Switch, Tristate Function
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Number Of Circuits: -
• Other names: PEB2245N-V12; PEB2245N-V12IN

Indirect access to the CFR, CSR, CM or CCM:
An indirect access is performed by reading/writing three consecutive bytes (first byte = control byte,
second byte = data byte, third byte = address byte) to/from IAR.
Bit 7
K2
D7
IA7
The bits K2 … K0 determine whether the CFR, the CSR, the CM or the CCM shall be accessed,
whether a write or read operation shall be performed and whether the first or the second memory
access shall be executed. (To describe a conference two accesses to the CCM are necessary). The
bits D7 … D0 contain the information which shall be written into the control memories or the indirect
registers. The address byte indicates which one of the indirect registers shall be accessed or in
which memory location the data shall be written. An exact definition is given in chapter Indirect
Access Register.
Before an indirect access is started, the Z- and B bits of the status register must be 0. With the first
instruction the Z-bit is set (see chapter Status Register). After the third instruction the MUSAC
accesses the memory location. This access requires maximally 900 ns. After the access is finished
the Z bit is reset.
Figure 16 a) illustrates a write operation on the IAR.
It is possible to read or write the direct access registers while an indirect access is in progress. Thus
a register may be read in the time intervals that separate the three sequential indirect access
instructions. Also, the current indirect access may be aborted by setting the MOD:RI. One indirect
register access has to be completed before the next one can be started.
To read the indirect registers or the CM two sequences of three instructions each have to be
programmed. In the first sequence the MUSAC is instructed which register of CM address to read.
The data transferred to the PEB 2245 in this first sequence is of no significance. With the first write
instruction STA:Z is set. After the first 3 instructions the MUSAC needs 900 ns to write the result to
the IAR. The status register bit Z is reset after maximally 900 ns. Then 3 read operations follow.
Again, STA:Z is set with the first read instruction. The 3 instructions read 3 bytes from the IAR.
Figure 16 b) shows this procedure. After the third read operation the PEB 2245 needs another
900 ns to reset the indirect access mechanism and the Z bit in the status register. In CCM read
accesses three sequences of three instructions (two write sequences and one read sequence; see
figure 16 c)) are necessary.
Semiconductor Group
K1
D6
IA6
K0
D5
IA5
0
D4
IA4
0
D3
IA3
DI0
D2
IA2
31
D9
D1
IA1
D8
D0
IA0
Bit 0
Control Byte
Data Byte
Address Byte
PEB 2245