DS3172+ Maxim Integrated Products, DS3172+ Datasheet - Page 128

• Manufacturer Part Number: DS3172+
• Description: IC TXRX DS3/E3 DUAL 400-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3172+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 2
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 328mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 400-BGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 15: Global Write Mode (GWRM) This bit enables the global write mode. When this bit is set, a write to the
register of any port will write to the same register in all the ports. Reading the registers of any port is not supported
and will read back undefined data.
Bit 14: INT pin mode (INTM) This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
Bit 7: Transmit Manual Error Insert (TMEI) This bit is used insert an error in all ports configured for global error
insertion. An error(s) is inserted at the next opportunity when this bit transitions from low to high. The
GL.CR1.MEIMS bit must be clear for this bit to operate.
Bit 6: Transmit Manual Error Insert Select (MEIMS) This bit is used to select the source of the global manual
error insertion signal
Bits 5 and 4: Global Performance Monitor Update Mode (GPM[1:0]) These bits select the global performance
monitor register update mode.
Bit 3: Global Performance Monitor Update Register (PMU) This bit is used to update all of the performance
monitor registers configured to use this bit. When this bit is toggled from low to high the performance registers
configured to use this signal will be updated with the latest count value from the counters, and the counters will be
reset. The bit should remain high until the performance register update status bit (GL.SR.PMS) goes high, then it
should be brought back low which clears the PMS status bit.
Bit 2: Latched Status Bit Clear on Read Enable (LSBCRE). This signal determines when latched status register
bits are cleared.
Bit 1: Reset Data Path (RSTDP). When this bit is set, it will force all of the internal data path registers in all ports
to their default state. This bit must be set high for a minimum of 100ns. See the
Section 10.3. Note: The default state is a 1 (after a general reset, this bit will be set to one).
0 = Normal write mode
1 = Global write mode
0 = Pin is high impedance when not active
1 = Pin drives high when not active
0 = Global error insertion using TMEI bit
1 = Global error insertion using the GPIO6 pin
00 = Global PM update using the PMU bit
01 = Global PM update using the GPIO8 pin
1x = One second PM update using the internal one second counter
0 = Latched status register bits are cleared on a write
1 = Latched status register bits are cleared on a read
0 = Normal operation
1 = Force all data path registers to their default values
GWRM
TMEI
15
0
7
0
MEIMS
INTM
14
0
6
0
GL.CR1
Global Control Register 1
002h
RESERVED
GPM1
13
0
5
0
GPM0
12
--
0
0
4
128
RESERVED
PMU
11
0
3
0
RESERVED
LSBCRE
10
Reset and Power-Down
0
2
0
RESERVED
RSTDP
9
0
1
1
RESERVED
RST
section in
8
0
0
0