DS2174Q+ Maxim Integrated Products, DS2174Q+ Datasheet - Page 4

• Manufacturer Part Number: DS2174Q+
• Description: IC BERT ENHANCED 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2174Q+

• Function: Enhanced Bit Error Rate Tester (EBERT)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Error Counter, Pattern Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

1. GENERAL OPERATION
1.1 Pattern Generation
1.1.1 Polynomial Generation
The DS2174 has a tap select register that can be used as a mask to tap up to 32 bits in the feedback path
of the polynomial generator. It also features a seed register that can be used to preload the polynomial
generator with a seed value. This is done on the rising edge of TL in Control Register 1.
The DS2174 generates polynomial patterns of any length up to and including 2
standard polynomials can be programmed using the control registers. The polynomial is generated using a
shift register of programmable length and programmable feedback tap positions. The user has access to
all combinations of pattern length and pattern tap location to generate industry-standard polynomials or
other combinations as well. In addition, the QRSS pattern described in T1.403 is described by the
polynomial 2
whenever the next 14 bits are 0.” Setting the QRSS bit in Control Register 1 causes the pattern generator
to enforce this rule.
1.1.2 Repetitive Pattern Generation
In addition to polynomial patterns, the DS2174 generates repetitive patterns of considerable length. The
programmer has access to 512 bytes of memory for storing pattern. The pattern length bits PL0 through
PL8, located at addresses 02h and 03h, are used to program the length of the repetitive pattern. Memory is
addressed indirectly and is used to store the pattern. Data can be sent MSB or LSB first as it appears in
the memory.
Repetitive patterns can include simple patterns such as 3 in 24, but the additional memory can be used to
store patterns such as DDS-n patterns or T1-n patterns. Repetitive patterns are stored in increments of 8
bits. To generate a repetitive pattern that is 12 bits long (3 nibbles), the pattern is written twice such that
the pattern is 24 bits long (3 bytes), and repeats twice in memory. The same is true when the device is
used in serial mode: a 5-bit pattern is written to memory 5 times. For example,
20
To generate a 00001 pattern at the serial output, write these bytes to memory:
– 1. This pattern has the additional requirement that “an output bit is forced to a 1
RAM ADDRESS
00h
01h
02h
03h
04h
BINARY CODE
4 of 24
00010000
01000010
00001000
00100001
10000100
HEX CODE
10h
42h
08h
21h
84h
32
- 1. All of the industry-