DS2174Q+ Maxim Integrated Products, DS2174Q+ Datasheet - Page 11

• Manufacturer Part Number: DS2174Q+
• Description: IC BERT ENHANCED 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2174Q+

• Function: Enhanced Bit Error Rate Tester (EBERT)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Error Counter, Pattern Generator and Detector
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

3. CONTROL REGISTERS
Control Register 1 (Address = 0h)
SYNCE
SYMBOL
(MSB)
RSYNC
SYNCE
LPBK
QRSS
LSB
LC
TL
PS
RSYNC
SYNC Enable
0 = Auto resync enabled
1 = Auto resync disabled
Initiate Manual Resync Process. A rising edge causes the device to go
out of sync and begin resynchronization process.
Latch Count Registers. A rising edge copies the bit count and bit error
count accumulators to the appropriate registers. The accumulators are
then cleared.
Transmit/Receive Loopback Select
0 = Loopback disabled
1 = Loopback enabled
Zero Suppression Select. Forces a 1 into the pattern whenever the next
14 bit positions are all 0’s. Should only be set when using the QRSS
pattern.
0 = Disable 14 zero suppression
1 = Enable 14 zero suppression per T1.403
Pattern Select
0 = Pseudorandom pattern
1 = Repetitive pattern
LSB/MSB
0 = Repetitive pattern data is transmitted/received MSB first
1 = Repetitive pattern data is transmitted/received LSB first
Transmit Load. A rising edge causes the transmit shift register to be
loaded with the seed value.
LC
LPBK
FUNCTION
11 of 24
QRSS
PS
LSB
(LSB)
TL