DS2172TN+T&R Maxim Integrated Products, DS2172TN+T&R Datasheet - Page 11

• Manufacturer Part Number: DS2172TN+T&R
• Description: IC BIT ERROR RATE TESTER 32TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS2172TN+T&R

• Function: Bit Error Rate Tester (BERT)
• Number Of Circuits: 1
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Interface: -
• Other names: 90-2172T+NTR

NOTES FOR TABLES 4 AND 5:
1. PTR = Polynomial Tap Register (address = 05)
2. PLR = Pattern Length Register (address = 04)
3. PSR3 = Pattern Set Register 3 (address = 00)
4. PSR2 = Pattern Set Register 2 (address = 01)
5. PSR1 = Pattern Set Register 1 (address = 02)
6. PSR0 = Pattern Set Register 0 (address = 03)
7. TINV = Transmit Data Inversion Select Bit (EIR.5)
8. RINV = Receive Data Inversion Select Bit (EIR.4)
9. For the 2
8.0 BIT COUNT REGISTERS
The Bit Count Registers (BCR3 to BCR0) comprise a 32-bit count of bits (actually RCLK cycles)
received at RDATA. BC31 is the MSB of the 32-bit count. The bit counter increments for each cycle of
RCLK when input pin RDIS is low. The bit counter is disabled during loss of SYNC. The Status Register
bit BCOF is set when this 32-bit register overflows. Upon an overflow condition, the user must clear the
BCR by either toggling the LC bit or pin. The DS2172 latches the bit count into the BCR registers and
clears the internal bit count when either the PCR.4 bit or the LC input pin toggles from low to high. The
bit count and bit error count (available via the BECRs) are used by an external processor to compute the
BER performance on a loop or channel basis.
BIT COUNT REGISTERS
9.0 BIT ERROR COUNT REGISTERS
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,
the user must clear the BECR by either toggling the LC bit or pin. The DS2172 latches the bit error count
into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC input
pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by an
external processor to compute the BER performance on a loop or channel basis.
BIT ERROR COUNT REGISTERS
(MSB)
(MSB)
BEC31
BEC23
BEC15
BC31
BC23
BC15
BEC7
BC7
2
32
- 1.
BC30
BC22
BC14
BC6
BEC30
BEC22
BEC14
BEC6
32
-1 pattern, the random pattern actually repeats every (4093 x 2
BC29
BC21
BC13
BC5
BEC29
BEC21
BEC13
BEC5
BC28
BC20
BC12
BC4
BEC28
BEC20
BEC12
BEC4
BC27
BC19
BC11
BC3
BEC27
BEC19
BEC11
BEC3
BC26
BC18
BC10
BC2
11 of 22
BEC26
BEC18
BEC10
BEC2
BC25
BC17
BC9
BC1
BEC25
BEC17
BEC9
BEC1
(LSB)
BC24
BC16
BC8
BC0
BEC24
BEC16
BEC8
BEC0
(LSB)
20
BCR1 (addr.=0A Hex)
BCR0 (addr.=0B Hex)
) + 1046529 bits instead of
BCR3 (addr.=08 Hex)
BCR2 (addr.=09 Hex)
BECR3 (addr.=0C Hex)
BECR2 (addr.=0D Hex)
BECR1 (addr.=0E Hex)
BECR0 (addr.=0F Hex)
DS2172