PEB3265H-V13 Infineon Technologies, PEB3265H-V13 Datasheet
PEB3265H-V13
Specifications of PEB3265H-V13
PEB3265H-V13IN
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PEB3265H-V13 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... FSC hold time ( t FSC hold time Page 52 Chapter 8.1 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com. 2000-11-09 Data Sheet DS1 “Functional Overview” completely overworked. ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6.4.3.1 Single-Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol SLICOFI-2/-2S/-2S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2 Pin ...
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Preliminary Preface Synonyms To simplify matters, the following synonyms are used: SLICOFI-2x Synonym used for all codec versions SLICOFI-2/-2S/-2S2 SLIC: Synonym used for all SLIC versions SLIC-S, SLIC-S2, SLIC-E, SLIC-E2 and SLIC-P Organization of this Document This Data Sheet is ...
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Preliminary 1 Overview The Subscriber Line Interface Circuit SLICOFI- highly flexible two channel codec solution for analog line circuits. The SLICOFI-2x is programmable via software and can be adapted to all different standards worldwide. DuSLIC Architecture The SLICOFI-2 ...
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Preliminary Dual Channel Subscriber Line Interface Codec Filter SLICOFI-2x Version 1.3 1.1 Features SLICOFI-2 • Fully programmable dual-channel codec • Programmable battery feeding with capability for driving long loops • Internal balanced/unbalanced ringing capability ( Vrms balanced / ...
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Preliminary 1.2 Features SLICOFI-2S/-2S2 • Fully programmable dual-channel codec • Programmable battery feed with capability for driving long loops • Internal balanced ringing capability Vrms • External ringing support • Ground/loop start signaling • Polarity reversal • ...
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Preliminary 1.3 Logic Symbol ITA ITB Line ITACA current ITACB ILA ILB VCMITA VCMITB DCPA DC DCPB loop DCNA DCNB CDCPA CDCNA CDCPB CDCNB VCM VCMS ACPA ACPB AC ACNA loop ACNB C1A C1B Logic C2A control C2B IO1A IO2A ...
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Preliminary 2 Pin Descriptions 2.1 Pin Diagram C1A ILA ITACA ITA VCMITA VDDR GNDR VCMS VCM CREF SELCLK VCMITB ITB ITACB ILB C1B 1 Figure 2 Pin Configuration SLICOFI-2/-2S/-2S2 (top view) Data Sheet PEB 3265 PEB 3264 PEB 3264-2 6 ...
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Preliminary Table 1 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 Pin Sym- Input (I) No. bol Output (O) 1 C2B O 2 DCPB O 3 CDCPB I/O 4 CDCNB I/O 5 DCNB O 6 ACPB O 7 ACNB O 8 VDDB Power ...
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Preliminary Table 1 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d) Pin Sym- Input (I) No. bol Output ( DOUT O 19 DCL I PCLK DRB I 21 SEL24 I DRA I 22 MCLK I ...
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Preliminary Table 1 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d) Pin Sym- Input (I) No. bol Output (O) 32 PCM/ I IOM-2 33 RSYNC I 34 RESET I 35 TEST I 36 IO4A I/O 37 IO3A I/O 38 IO2A I/O 39 ...
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Preliminary Table 1 Pin Definitions and Functions SLICOFI-2/-2S/-2S2 (cont’d) Pin Sym- Input (I) No. bol Output (O) 52 ITA I 53 VCMITA I 54 VDDR Power 55 GNDR Power 56 VCMS O 57 VCM O 58 CREF I/O 59 SELCLK ...
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Preliminary 3 Functional Description 3.1 Functional Overview 3.1.1 Basic Functions available for all SLICOFI-2x Codecs The functions described in this chapter are integrated in all DuSLIC chip sets (see Figure 3 for SLICOFI-2S/-2S2 and All BORSCHT functions are integrated: • ...
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Preliminary The characteristics for the two voice channels within SLICOFI-2x can be programmed independently of each other. The DuSLICOS software is provided to automate calculation of coefficients to match different requirements. DuSLICOS also verifies the calculated coefficients. 3.1.2 Additional Functions ...
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Preliminary SLIC-S/-S2 Current Sensor & Offhook Detection TIP Gain Channel A RING V /V Control BAT H switch Logic SLIC-S/-S2 Channel B Current Sensor & Offhook Detection TIP Gain RING V /V Control BAT H switch Logic * not available ...
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Preliminary 3.2 Block Diagrams Figure 5 shows the internal block structure of all SLICOFI-2x codec versions available. The Enhanced Digital Signal Processor (EDSP) realizing the add-on funtions integrated in the SLICOFI-2 (PEB 3265) device. PEB 3265 / PEB 3264 / ...
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Preliminary 3.2.1 DTMF Generation The SLICOFI-2x offers programmable DTMF generation for both channels by using the internal tone generators. 3.2.2 DTMF Detection (SLICOFI-2 only) Both channels (A and B) of the SLICOFI-2 device have a powerful built-in DTMF decoder that ...
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Preliminary Table 2 Performance Characteristics of the DTMF Decoder Algorithm (cont’d) Characteristic 13 Interference rejection 480 Hz for valid DTMF recognition 14 Gaussian noise influence Signal level – 22 dBm0, SNR = Pulse noise ...
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Preliminary 3.2.3 Caller ID Generation (SLICOFI-2 only) The SLICOFI-2 contains a FSK generation unit for sending Caller ID information. SLICOFI-2 FSK Generation Different countries use different standards to send Caller ID information. The SLICOFI-2 chip is compatible with the widely ...
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Preliminary 4 Operating Modes for the DuSLIC Chip Set Table 4 Operating Modes for SLICOFI-2x and SLICS SLICOFI-2x Mode SLIC-S/ SLIC-S2 Sleep (SL) – Power Down PDRH Resistive (PDR) Power Down PDH High Impedance (PDH) Active High ACTH (ACTH) Active ...
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Preliminary Table 4 Operating Modes for SLICOFI-2x and SLICS (cont’d) SLICOFI-2x Mode SLIC-S/ SLIC-S2 Ground Start HIT 3) Ring Pause ACTR 1) CIDD = Data Downstream Command/Indication Channel Byte (IOM-2 interface) CIOP = Command/Indication Operation For SLICOFI-2x command structure and ...
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Preliminary 4.1 SLICOFI-2S/-2S2 and SLIC-S/-S2 Interface The SLIC-S/-S2 (PEB 4264/-2) operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 5 SLIC-S/-S2 Interface Code 1) C1 (Pin 18 ...
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Preliminary 4.2 SLICOFI-2 and SLIC-E/-E2 Interface The SLIC-E/-E2 (PEB 4265/-2) operates in the following modes controlled by a ternary logic signal at the C1 and C2 input: Table 7 SLIC-E/-E2 Interface Code “Overtemp” ...
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Preliminary 4.3 SLICOFI-2 and SLIC-P Interface The SLIC-P (PEB 4266) operates in the following modes controlled by a ternary logic signal at the C1, C2 inputs and a binary logic signal at C3 input : Table 9 SLIC-P Interface Code ...
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Preliminary Table 10 SLIC-P Modes (cont’d) SLIC Mode Mode Description HIT High Impedance on TIP HIR High Impedance on RING ROR Ring on RING ROT Ring on TIP For the usage of the SLIC-P modes see the DuSLIC Data Sheet. ...
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Preliminary 5 Signal Path and Test Loops The following figures show the main AC and DC signal path and the integrated analog and digital loops of SLICOFI-2, SLICOFI-2S and SLICOFI-2S2. Please note the interconnections between the AC and DC pictures ...
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Preliminary LM-SEL[3: IO3 PD-DC-PR IO4 PREFI IO4 – IO3 VDD Offset PD-DCBUF PC-POFI-HI DCN/DCP DC BUF Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 7 DC Test Loops SLICOFI-2 ...
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Preliminary 5.2 Test Loops SLICOFI-2S/-2S2 The AC test loops for SLICOFI-2S since Teletax (TTX) is not available with SLICOFI-2S2. The DC test loops are identical. AC-DLB-32K COX16 a AX2 HPX2 HPX-DIS AX-DIS AR-DIS b AR2 COR-64 ITAC Programmable via CRAM ...
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Preliminary AC-DLB-32K COX16 a AX2 HPX2 HPX-DIS AX-DIS AR-DIS b AR2 COR-64 ITAC Programmable via CRAM Not Programmable ACN/ACP Always available SWITCH Available only when bit SWITCH TEST- Figure 9 AC Test Loops SLICOFI-2S2 Data Sheet LPX FRX ...
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Preliminary PD-DC- PREFI PD-DCBUF PC-POFI-HI DCN/DCP DC BUF Programmable via CRAM Not Programmable Always available SWITCH Available only when bit SWITCH TEST- Figure 10 DC Test Loops SLICOFI-2S/-2S2 Data Sheet * ...
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Preliminary 6 Electrical Characteristics 6.1 Electrical Characteristics PEB 3264/PEB 3264-2/PEB 3265 6.1.1 Absolute Maximum Ratings 1) Parameter Supply pins (VDDi) referred to the corresponding ground pin (GNDi) Ground pins (GNDi) referred to any other ground pin (GNDj) Supply pins (VDDi) ...
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Preliminary Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional operation under these conditions is not guaranteed. Exposure to conditions beyond those indicated in the recommended operational conditions of this specification may ...
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Preliminary 6.1.4 Power Dissipation SLICOFI – 40 ° °C, unless otherwise stated DDD DDA DDB GNDA GNDB GNDR Parameter Symbol 1) V supply ...
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Preliminary 6.1.5 Power Dissipation SLICOFI-2S/-2S2 T = – 40 ° °C, unless otherwise stated DDD DDA DDB GNDA GNDB GNDR Parameter Symbol 1) V supply ...
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Preliminary 6.1.6 Digital Interface T = – unless otherwise stated 3 DDD DDA/B Parameter For all input pins (including IO pins): Low-input pos.-going High-input neg.-going Input ...
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Preliminary Figure 11 Hysteresis for Input Pins 6.1.7 Miscellaneous Characteristics T = – 40 ° °C, unless otherwise stated. A Parameter Symbol Leakage all digital input and I input/output pins all analog input pins Comparator Thresholds Off Hook ...
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Preliminary 6.2 AC Transmission SLICOFI-2/-2S/-2S2 The specification is based on the subscriber linecard requirements. The proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) requires the consideration of the complete analog environment of the SLICOFI-2x device. Functionality ...
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Preliminary Table 12 AC Transmission (cont’d) Parameter Symbol Frequency Response Receive loss G RAF Frequency variation Transmit loss G XAF Frequency variation Gain Tracking (see Figure 14 Transmit gain G XAL Signal level variation Receive gain G RAL Signal level ...
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Preliminary Table 12 AC Transmission (cont’d) Parameter Symbol Group Delay (see Figure Transmit delay absolute Receive delay absolute Group delay D XR distortion, Receive and Transmit, relative to 1500 Hz, (see Figure 16) Overload compression A/D ...
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Preliminary Table 12 AC Transmission (cont’d) Parameter Symbol Distortion (Sinusoidal Test Method) Signal to total STD X distortion Transmit Signal to total STD R distortion Receive Power Supply Rejection Ratio Power supply PSRR rejection ratio V Receive – ...
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Preliminary Figure 12 Overload Compression A Figure 13 Insertion Loss Data Sheet 3 Fundamental Input Power (dBm0 (B) 768 ...
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Preliminary 6.2.1 Gain Tracking (Receive or Transmit) The gain deviations stay within the limits in the figures below 1 0.5 + 0.25 - 0. -70 -60 ...
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Preliminary 6.2.2 Group Delay Minimum delays occure when the SLICOFI-2x is operating with disabled Frequency Response Receive and Transmit filters including the delay through A/D and D/A converters. Specific filter programming may cause additional group delays. Absolute Group delay also ...
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Preliminary 6.3 DC Characteristics T = – 40 ° °C, unless otherwise stated. A Table 13 DC Characteristics Parameter Symbol Insertion Loss A-D PCM OUT (see Figure 17) D (see Figure 17 ...
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Preliminary 6.4 SLICOFI-2/-2S/-2S2 Timing Characteristics T = – 40 ° °C, unless otherwise stated. A 6.4.1 Input/Output Waveform for AC Tests V – 0.5 V Figure 18 Waveform for ...
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Preliminary 6.4.2 MCLK/FSC Timing t MCLK 50% MCLK t t FSC_S FSC_H FSC Figure 19 MCLK / FSC-Timing Parameter Symbol 1) Period MCLK t 512 kHz ± 100 ppM 1536 kHz ± 100 ppM 2048 kHz ± 100 ppM 4096 ...
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Preliminary 6.4.3 PCM Interface Timing 6.4.3.1 Single-Clocking Mode t PCLK 50% PCLK t FSC_H2 FSC DRA/B DXA/B TCA/B Figure 20 PCM Interface Timing - Single-Clocking Mode Parameter Symbol 1) Period PCLK t PCLK high time Period FSC ...
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Preliminary Parameter Symbol t 2) DXA/B delay time DXA/B delay time t to high Z t TCA/B delay time on t TCA/B delay time off 1) The PCLK frequency must be an integer multiple of the FSC frequency. 2) All ...
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Preliminary Parameter Symbol t 1) Period PCLK t PCLK high time 1) t Period FSC t FSC setup time t FSC hold time 1 FSC hold time DRA/B setup time t DRA/B hold time t 2) DXA/B ...
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Preliminary 6.4.4 Microcontroller Interface Timing t DCLK 50% DCLK t CS_S DIN_S DIN_H DIN DOUT Figure 22 Microcontroller Interface Timing Parameter Symbol t Period of DCLK DCLK t DCLK high time DCLKh t CS setup time CS_s ...
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Preliminary 6.4.5 IOM-2 Interface Timing 6.4.5.1 Single-Clocking Mode t DCL 50% DCL t FSC_H2 FSC DD DU Figure 23 IOM-2 Interface Timing – Single-Clocking Mode Parameter Symbol 1) t Period DCL DCL t DCL high time DCLh 1) t Period ...
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Preliminary 6.4.5.2 Double-Clocking Mode t DCL 50% DCL t FSC_S t t FSC_H1 FSC_H2 FSC Figure 24 IOM-2 Interface Timing – Double-Clocking Mode Parameter Symbol 1) t Period DCL DCL t DCL high time DCLh 1) t ...
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Preliminary 7 Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package) Figure 25 PEB 3265, PEB 3264, PEB 3264-2 (SLICOFI-2x) Sorts of Packing Package outlines for tubes, trays etc. are contained in our data book “Package Information”. SMD = Surface Mounted ...
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Preliminary 8 Glossary 8.1 List of Abbreviations ACTL Active with ACTH Active with ACTR Active with ADC Analog Digital Converter AR Attenuation Receive AX Attenuation Transmit BP Band Pass CMP Compander Codec Coder Decoder COP Coefficient Operation CRAM Coefficient RAM ...
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Preliminary PDRHL Power Down Load Resistive on PDRRL Power Down Load Resisitve on PDRH Power Down Resistive on PDRR Power Down Resistive on POFI Post Filter PREFI Antialiasing Pre Filter RECT Rectifier (Testloops, Levelmetering) SLIC Subscriber Line Interface Circuit (synonym ...
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Preliminary 9 Index A Active 23 Active High 18 Active Low 18 Active Ring 18 Active with HIR 18 Active with HIT 18 Active with Metering 18 B Battery feed Caller ID 3, 12, 17 Coding ...
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