SI3220-G-GQ Silicon Laboratories Inc, SI3220-G-GQ Datasheet - Page 20
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SI3220-G-GQ
Manufacturer Part Number
SI3220-G-GQ
Description
IC PROSLIC/CODEC DUAL 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet
1.SI3200-G-FSR.pdf
(112 pages)
Specifications of SI3220-G-GQ
Package / Case
64-TQFP, 64-VQFP
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
65mA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Product
SLIC
Supply Voltage (min)
3.13 V
Supply Current
22 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Channels
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3220-G-GQ
Manufacturer:
CREATIVE
Quantity:
99
Company:
Part Number:
SI3220-G-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
SI3220-G-GQR
Manufacturer:
SILICON
Quantity:
15 000
Company:
Part Number:
SI3220-G-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Si3220/25 Si3200/02
Table 14. Switching Characteristics—GCI Highway Serial Interface
(V
20
Parameter
PCLK Period (2.048 MHz PCLK Mode)
PCLK Period (4.096 MHz PCLK Mode)
FSYNC Period
PCLK Duty Cycle Tolerance
FSYNC Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
Delay Time, PCLK Rise to DTX Tristate
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
FSYNC Pulse Width
Notes:
DD
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
, V
DD1
fall times are referenced to the 20% and 80% levels of the waveform.
– V
FSYNC
1
PCLK
DD4
Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
DRX
DTX
2
=
3.13 to 5.25 V, T
t
su1
Frame 0,
A
Bit 0
t
d1
=
0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade)
3
Frame 0,
Symbol
t
Bit 0
h1
t
t
t
t
t
jitter
t
t
t
t
t
su1
su2
t
wfs
dty
t
t
d1
d2
d3
t
t
h1
h2
fs
p
p
r
f
Rev. 1.3
t
Conditions
su2
t
d2
t
p
Test
t
h2
t
fs
Min
t
40
25
20
25
20
—
—
—
—
—
—
—
—
—
p
/2
t
r
IH
=
V
O
Typ
488
244
125
– 0.4 V, V
50
—
—
—
—
—
—
—
—
—
—
—
IL
t
=
f
±120
Max
t
d3
60
25
25
20
20
20
—
—
—
—
—
—
—
—
0.4 V, rise and
Units
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%