SI3225-BQ Silicon Laboratories Inc, SI3225-BQ Datasheet - Page 79
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SI3225-BQ
Manufacturer Part Number
SI3225-BQ
Description
IC SLIC/CODEC DUAL-CH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Specifications of SI3225-BQ
Package / Case
*
Function
Subscriber Line Interface Concept (SLIC), CODEC
Interface
GCI, PCM, SPI
Number Of Circuits
2
Voltage - Supply
3.3V, 5V
Current - Supply
65mA
Power (watts)
941mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
Battery Switching, BORSCHT Functions, DTMF Generation and Decoding, FSK Tone Generation, Modem and Fax Tone Detection
Product
SLIC
Supply Voltage (min)
3.13 V
Supply Current
22 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Channels
2
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI3225-BQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
3.29. PCM Interface
The
programmable interface for the transmission and
reception of digital PCM samples. PCM data transfer is
controlled by the PCLK and FSYNC inputs, PCM Mode
Select,
PCMTXLO), and PCM Receive Start Count (PCMRXHI/
PCMRXLO) registers. The interface can be configured
to support from 4 to 128 8-bit timeslots in each frame.
This corresponds to PCLK frequencies of 256 kHz to
8.192 MHz
1.536 MHz, and 1.544 MHz are also available for T1
and E1 support.) Timeslots for data transmission and
reception are independently configured with the
PCMTXHI, PCMTXLO, PCMRXHI, and PCMRXLO.
Special consideration must be given to the PCM
Receive Start Count (PCMRXHI / PCMRXLO) registers.
Changing the PCMRXHI (Reg. 57), PCMRXLO (Reg.
56) on-the-fly while the Si3220/25 is actively passing
audio can cause the digital impedance synthesis block
to perform improperly producing an audible loud white
noise signal across TIP and RING.
To ensure proper device operation, the RX timeslot
registers (PCMRXHI and PCMRXLO, registers 56–57)
should be set during the initialization procedure
immediately after power-up and prior to both enabling
the PCM bus and setting the linefeed to the active state.
The TX timeslot registers (PCMTXHI and PCMTXLO,
registers 54–55) may be changed at any time to
establish audio connections on the PCM bus.
Setting the correct starting point of the data configures
the part to support long FSYNC and short FSYNC
variants, IDL2 8-bit, 10-bit, and B1 and B2 channel time
Dual
PCM
ProSLIC
in
PCLK_CNT
Transmit
power-of-2
FSYNC
PCLK
DRX
DTX
Figure 51. Example, Timeslot 1, Short FSYNC (TXS/RXS = 1)
devices
HI-Z
Start
0
increments.
1
contain
Count
MSB
MSB
2
3
(PCMTXHI/
a
4
(768 kHz,
flexible
5
6
Rev. 1.3
7
slots. DTX data is high-impedance except for the
duration of the 8-bit PCM transmit. DTX returns to high-
impedance on the negative edge of PCLK during the
LSB or on the positive edge of PCLK following the LSB.
This is based on the setting of the PCMTRI bit of the
PCM Mode Select register. Tristating on the negative
edge allows the transmission of data by multiple
sources in adjacent timeslots without the risk of driver
contention. In addition to 8-bit data modes, a 16-bit
mode is provided for testing. This mode can be
activated via the PCMF bits of the PCM Mode Select
register.
PCMRXHI/PCMRXLO register greater than the number
of PCLK cycles in a sample period stops data
transmission because neither PCMTXHI/PCMTXLO nor
PCMRXHI/PCMRXLO equal the PCLK count. Figures
51–54 illustrate the usage of the PCM highway interface
to adapt to common PCM standards.
As shown in the application schematics in Figures 12
and 13, a pulldown resistor is required on the DTX pin.
A pullup resistor is not allowed on the DTX pin.
Additionally, the PCLK frequency should be chosen
such that there is at least one empty timeslot (hi-Z
timeslot) per 8 kHz frame. If a PCLK is chosen such that
DTX has valid data during the entire frame, choose the
next higher valid PCLK frequency to ensure one or
more empty timeslots in each frame. If an application
requires heavy capacitive loading on the DTX pin, or
more than eight Si322x devices connected to the same
PCM bus, consult your local Silicon Laboratories sales
representative to determine what value of pulldown
resistor should be used.
8
LSB
LSB
9
10
Si3220/25 Si3200/02
Setting
11
12
HI-Z
13
the
14
15
PCMTXHI/PCMTXLO
16
17
18
79
or