DS21354LC1+ Maxim Integrated Products, DS21354LC1+ Datasheet - Page 4

• Manufacturer Part Number: DS21354LC1+
• Description: IC TXRX E1 3.3V 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21354LC1+

• Function: Single-Chip Transceiver
• Interface: E1, HDLC
• Number Of Circuits: 1
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Includes: Remote and AIS Alarm Detector / Generator
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
LIST OF FIGURES
Figure 2-1. DS21354/554 Block Diagram ............................................................................................................................. 9
Figure 15-1. Basic External Analog Connections .............................................................................................................. 83
Figure 15-2. Optional Crystal Connection........................................................................................................................... 83
Figure 15-3. Jitter Tolerance................................................................................................................................................. 84
Figure 15-4. Jitter Attenuation .............................................................................................................................................. 84
Figure 15-5. Transmit Waveform Template ........................................................................................................................ 85
Figure 15-6. Protected Interface Example for the DS21554 ............................................................................................ 87
Figure 15-7. Protected Interface Example for the DS21354 ............................................................................................ 88
Figure 15-8. Typical Monitor Port Application .................................................................................................................... 89
Figure 16-1. JTAG Functional Block Diagram.................................................................................................................... 91
Figure 16-2. TAP Controller State Diagram........................................................................................................................ 94
Figure 17-1. IBO Basic Configuration Using Four SCTs .................................................................................................. 99
Figure 18-1. Receive-Side Timing...................................................................................................................................... 100
Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled)................................................................. 100
Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) .............................................. 101
Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) .............................................. 101
Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode ................................................................................ 102
Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode............................................................................. 103
Figure 18-7. Transmit-Side Timing .................................................................................................................................... 104
Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)................................................................ 104
Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) ............................................. 105
Figure 18-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled) ........................................... 105
Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode ............................................................................. 106
Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode.......................................................................... 107
Figure 18-13. G.802 Timing ................................................................................................................................................ 108
Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart ........................................................................ 109
Figure 18-15. DS21354/DS21554 Transmit Data Flow .................................................................................................. 110
Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1)........................................................................................... 113
Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1)................................................................................................. 113
Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1) ............................................................................................ 114
Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0).......................................................................................... 115
Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0) .......................................................................................... 116
Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0).................................................................................. 116
Figure 20-7. Motorola Bus Write AC Timing (BTS = 1/MUX = 0) .................................................................................. 116
Figure 20-8. Receive-Side AC Timing ............................................................................................................................... 118
Figure 20-9. Receive System Side AC Timing................................................................................................................. 119
Figure 20-10. Receive Line Interface AC Timing............................................................................................................. 120
Figure 20-11. Transmit-Side AC Timing............................................................................................................................ 122
Figure 20-12. Transmit System Side AC Timing.............................................................................................................. 123
Figure 20-13. Transmit Line Interface Side AC Timing................................................................................................... 123
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