DS21554L+ Maxim Integrated Products, DS21554L+ Datasheet - Page 61
DS21554L+
Manufacturer Part Number
DS21554L+
Description
IC TXRX E1 1-CHIP 5V 100-LQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2154LNA2.pdf
(124 pages)
Specifications of DS21554L+
Function
Single-Chip Transceiver
Interface
E1, HDLC, J1, T1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LQFP
Includes
Remote and AIS Alarm Detector / Generator
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex)
10.1.2.
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8-bit code
to be placed into each of the 32 E1 channels.
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address = 60 to 7F Hex)
(For brevity, only channel one is shown; see for other register address.)
TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER
(Address = A0 to A3 Hex)
(MSB)
SYMBOL
SYMBOL
SYMBOL
(MSB)
CH16
CH24
CH32
(MSB)
TIDR7
CH8
TIDR7
TIDR0
CH1 to
C7
CH32
C7
C0
Per-Channel Code Insertion
CH15
CH23
CH31
CH7
TIDR6
POSITION
C6
POSITION
POSITION
TCC1.0 to
TIDR.7
TIDR.0
TCC4.7
TC1.7
TC1.0
CH14
CH22
CH30
CH6
C5
TIDR5
MSB of the Code (this bit is transmitted first)
LSB of the Code (this bit is transmitted last)
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
Transmit Channel Code Insertion Control Bits
0 = do not insert data from the TC register into the transmit data stream
1 = insert data from the TC register into the transmit data stream
CH13
CH21
CH29
CH5
C4
TIDR4
CH12
CH20
CH28
CH4
61 of 124
C3
NAME AND DESCRIPTION
NAME AND DESCRIPTION
NAME AND DESCRIPTION
TIDR3
CH11
CH19
CH27
CH3
C2
TIDR2
CH10
CH18
CH26
CH2
C1
(LSB)
CH17
CH25
CH1
CH9
TIDR1
(LSB)
C0
TCC1 (A0)
TCC2 (A1)
TCC3 (A2)
TCC4 (A3)
TIDR0
(LSB)
TC1 (60)
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