IS43DR16160A-25EBLI ISSI, Integrated Silicon Solution Inc, IS43DR16160A-25EBLI Datasheet - Page 14

• Manufacturer Part Number: IS43DR16160A-25EBLI
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16160A-25EBLI

• Lead Free Status / Rohs Status: Compliant

IS43/46DR83200A, IS43/46DR16160A
IDD Specifications & Test Conditions (continued)
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of
5. For DDR2-667/800 testing, tCK in the Conditions should be interpreted as tCK(avg)
6. For A2 temperature grade with T
7. Definitions for IDD
LOW = Vin ≤ VILAC(max)
HIGH = Vin ≥ VIHAC(min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at VREF = VDDQ/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and inputs
14
Symbol
IDD4R
IDD5B
IDD6
IDD7
EMR(1) bits 10 and 11.
the values shown.
changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Conditions
Operating burst read current; All banks open, Continuous burst reads,
IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS =
tRASmax(IDD), tRP = tRP(IDD);
CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Burst refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval;
CKE is HIGH, CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Self refresh current;
CK and CK at 0 V; CKE ≤ 0.2 V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =
tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD),
tRCD = 1 x tCK(IDD);
CKE is HIGH, CS is HIGH between valid commands; Address bus
inputs are STABLE during DESELECTs;
Data pattern is same as IDD4R;
a
> 85
o
C, I
dd
2
p
and I
dd
3
p
(slow) are derated to 60% above the values shown, and I
Integrated Silicon Solution, Inc. — www.issi.com
x16
x16
x16
x16
x8
x8
x8
x8
DDR2-
800E
-25E
345
310
255
210
290
290
9
3
DDR2-
667D
300
275
245
195
280
280
-3D
9
3
dd
DDR2-
6
533C
is derated to x2 above
-37C
240
240
220
180
270
270
9
3
DDR2-
400B
190
190
200
170
265
265
-5B
9
3
05/24/2011
Units
Rev. B
mA
mA
mA
mA