KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 142

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Document Revision History
142
Revision
1
0
10/2007
07/2007
Date
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
• Adjusted maximum SYSCLK frequency down in
• Clarified notes to
• Added
• Clarified descriptions and added PCI/PCI-X to
• Removed support for 266 and 200 Mbps data rates per device erratum GEN-13 in
• Clarified Note 4 of
• Clarified the reference clock used in
• Corrected V
• Corrected V
• Removed DC parameters from
• Corrected V
• Corrected t
• Updated parameter descriptions for t
• Updated parameter descriptions for t
• Added LUPWAIT signal to
• Added LGTA signal to
• Corrected LUPWAIT assertion in
• Clarified the PCI reference clock in
• Added
• Added PBGA thermal information in
• Updated.”
• Updated
• Initial Release
device erratum GEN-13.
DDR2
Characteristics.”
Table
Timing Parameters (BV
(BV
Timing Parameters—PLL
and t
Signals (PLL Bypass
FC-PBGA with Full
DD
LBIXKH2
34, and
SDRAM.”
= 2.5 V)—PLL
Section 4.4, “PCI/PCI-X Reference Clock
Section 17.1, “Package
Table 84. Document Revision History (continued)
Table 83, “Part Numbering
MDC
IH
IL
IH
.
(max) in
(min) in
(min) in
Table
(min) in
Table 6, “EC_GTX_CLK125 AC Timing
Table 19, “DDR SDRAM Output AC Timing
Lid.”
35.
Mode).”
Enabled.”
Table 22, “GMII, MII, RMII, and TBI DC Electrical
Table 36, “MII Management DC Electrical
Table 23, “GMII, MII, RMII, TBI, RGMII, RTBI, and FIFO DC Electrical
Figure
DD
Table 37, “MII Management AC Timing
Bypassed.” Note that t
= 3.3 V)—PLL
Figure 23, “Local Bus Signals (PLL
25,
Parameters.”
Table
Figure
Figure 26
Section 14.2, “PCI/PCI-X AC Electrical
Nomenclature.”
Section 7.2, “DUART AC Electrical
Section 20.2, “Thermal for Version 2.1.1 and 2.1.2 Silicon
LBIVKH1
LBIVKH1
Substantive Change(s)
24,
26,
Table
Enabled” and
and
, t
, t
Figure 27
LBIVKH2
LBIVKL2
Table 9, “PLL Lock
25,
LBIVKL2
Figure
Table 5, “SYSCLK AC Timing
Timing.”
Table
, t
, t
and
LBIXKH1
28.
LBIXKH1
Table 40, “Local Bus Timing Parameters
and t
26,
Specifications.”
Figure
Table
LBIXKL2
Specifications.”
, and t
Enabled)” and
Specifications.”
, and t
Characteristics.”
28.
Times.”
27,
were previously labeled t
LBIXKL2
LBIXKH2
Table
Characteristics.”
Specifications.”
Specifications”
28,
Freescale Semiconductor
in
in
Figure 24, “Local Bus
Specifications” per
Table 42, “Local Bus
Table 40, “Local Bus
Table
Section 6, “DDR and
29,
Table
LBIVKH2
32,