KMPC8548EVTAUJC Freescale Semiconductor, KMPC8548EVTAUJC Datasheet - Page 126

• Manufacturer Part Number: KMPC8548EVTAUJC
• Manufacturer: Freescale Semiconductor

Specifications of KMPC8548EVTAUJC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Thermal
19.3
Table 78
ratio is determined by the binary value of LBCTL, LALE, and LGPL2 at power up, as shown in
19.4
Table 79
SYSCLK ratio in comparison to the memory bus clock speed.
20 Thermal
This section describes the thermal specifications of the MPC8548.
126
Note: Due to errata Gen 13, the max sys clk frequency should not exceed 100 MHz if the core clk frequency is below 1200 MHz.
CCB to SYSCLK
LBCTL, LALE, LGPL2
Ratio
Binary Value of
10
12
16
20
2
3
4
5
6
8
9
describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
shows the expected frequency values for the platform frequency when using a CCB clock to
Signals
e500 Core PLL Ratio
Frequency Options
000
001
010
011
Table 79. Frequency Options of SYSCLK with Respect to Memory Bus Speeds
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 7
16.66
333
e500 core:CCB Clock Ratio
400
500
25
Table 78. e500 Core to CCB Clock Ratio
Reserved
4:1
9:2
3:2
33.33
333
400
533
Platform/CCB Frequency (MHz)
41.66
333
375
417
500
SYSCLK (MHz)
LBCTL, LALE, LGPL2
66.66
Binary Value of
333
400
533
Signals
100
101
110
111
333
415
500
83
100
400
500
e500 core:CCB Clock Ratio
Freescale Semiconductor
111
333
445
2:1
5:2
3:1
7:2
Table
133.33
400
533
78.