P89LPC932A1FHN-S NXP Semiconductors, P89LPC932A1FHN-S Datasheet - Page 48

• Manufacturer Part Number: P89LPC932A1FHN-S
• Description: MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 28-Pin HVQFN EP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89LPC932A1FHN-S

• Package: 28HVQFN EP
• Device Core: 80C51
• Family Name: 89LP
• Maximum Speed: 18 MHz
• Ram Size: 768 Byte
• Program Memory Size: 8 KB
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 26
• Interface Type: I2C/SPI/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 2

NXP Semiconductors
10. Dynamic characteristics
Table 9.
V
T
P89LPC932A1_3
Product data sheet
Symbol
f
f
f
T
f
Glitch filter
t
t
External clock
t
t
t
t
Shift register (UART mode 0)
t
t
t
t
t
SPI interface
f
T
t
OSC(RC)
OSC(WD)
osc
CLKLP
gr
sa
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
SPI
SPILEAD
amb
DD
cy(CLK)
SPICYC
= 2.4 V to 3.6 V unless otherwise specified.
= 40 C to +85 C for industrial applications, unless otherwise specified.
Dynamic characteristics (12 MHz)
Parameter
internal RC oscillator frequency
internal watchdog oscillator
frequency
oscillator frequency
clock cycle time
low power select clock frequency
glitch rejection
signal acceptance
clock HIGH time
clock LOW time
clock rise time
clock fall time
serial port clock cycle time
output data set-up to clock rising
edge time
output data hold after clock rising
edge time
input data hold after clock rising
edge time
input data valid to clock rising
edge time
SPI operating frequency
SPI cycle time
SPI enable lead time
slave
master
slave
master
2.0 MHz (slave)
Conditions
see
P1.5/RST pin
any pin except
P1.5/RST
P1.5/RST pin
any pin except
P1.5/RST
see
see
see
see
see
see
see
see
see
see
26,
see
Rev. 03 — 12 March 2007
27
Figure 23
Figure 23
Figure 23
Figure 23
Figure 23
Figure 22
Figure 22
Figure 22
Figure 22
Figure 22
Figure
Figure
8-bit microcontroller with accelerated two-clock 80C51 core
24, 25,
26,
27
16T
13T
6 CCLK
4 CCLK
7.189
Min
280
125
150
250
83
50
33
33
cy(CLK)
cy(CLK)
0
0
0
-
-
-
-
-
-
-
Variable clock
[1][2]
T
T
cy(CLK)
T
cy(CLK)
cy(CLK)
CCLK 6
CCLK 4
7.557
Max
480
12
50
15
P89LPC932A1
8
8
8
0
-
-
-
-
-
-
-
-
-
+ 20
t
t
CHCX
CLCX
f
7.189
1333
1083
osc
Min
280
125
150
500
333
250
50
33
33
0
© NXP B.V. 2007. All rights reserved.
-
-
-
-
-
-
-
-
-
-
= 12 MHz Unit
7.557 MHz
Max
480
103
2.0
3.0
50
15
8
8
0
-
-
-
-
-
-
-
-
-
-
-
-
-
48 of 64
kHz
MHz
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns