LPC2420FBD208-S NXP Semiconductors, LPC2420FBD208-S Datasheet - Page 41
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LPC2420FBD208-S
Manufacturer Part Number
LPC2420FBD208-S
Description
MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2460FBD208551.pdf
(79 pages)
Specifications of LPC2420FBD208-S
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Ram Size
82 KB
Operating Supply Voltage
3.3 V
Data Bus Width
16|32 Bit
Program Memory Type
ROMLess
Number Of Programmable I/os
160
Interface Type
I2C/I2S/SPI/SSP/UART/USB
On-chip Adc
8-chx10-bit
On-chip Dac
1-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
NXP Semiconductors
LPC2420_60_5
Preliminary data sheet
7.24.1.3 RTC oscillator
7.24.2 PLL
7.24.3 Wake-up timer
PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The
clock frequency for each peripheral can be selected individually and is referred to as
PCLK. Refer to
The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the
RTC oscillator can be used to drive the PLL and the CPU.
The PLL accepts an input clock frequency in the range of 32 kHz to 24 MHz. The input
frequency is multiplied up to a high frequency, then divided down to provide the actual
clock used by the CPU and the USB block.
The PLL input, in the range of 32 kHz to 24 MHz, may initially be divided down by a value
‘N’, which may be in the range of 1 to 256. This input division provides a wide range of
output frequencies from the same input frequency.
Following the PLL input divider is the PLL multiplier. This can multiply the input divider
output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the
range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to
550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a
phase-frequency detector to compare the divided CCO output to the multiplier input. The
error value is used to adjust the CCO frequency.
The PLL is turned off and bypassed following a chip Reset and by entering Power-down
mode. PLL is enabled by software only. The program must configure and activate the PLL,
wait for the PLL to lock, then connect to the PLL as a clock source.
The LPC2420/2460 begins operation at power-up and when awakened from Power-down
and Deep-power down modes by using the 4 MHz IRC oscillator as the clock source. This
allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
When the main oscillator is initially activated, the wake-up timer allows software to ensure
that the main oscillator is fully functional before the processor uses it as a clock source
and starts to execute instructions. This is important at power on, all types of Reset, and
whenever any of the aforementioned functions are turned off for any reason. Since the
oscillator and other functions are turned off during Power-down and Deep power-down
modes, any wake-up of the processor from Power-down modes makes use of the
wake-up timer.
The wake-up timer monitors the crystal oscillator to check whether it is safe to begin code
execution. When power is applied to the chip, or when some event caused the chip to exit
Power-down mode, some time is required for the oscillator to produce a signal of sufficient
amplitude to drive the clock logic. The amount of time depends on many factors, including
the rate of V
characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g.,
capacitors), and the characteristics of the oscillator itself under the existing ambient
conditions.
DD(3V3)
Section 7.24.2
ramp (in the case of power on), the type of crystal and its electrical
Rev. 05 — 24 February 2010
for additional information.
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
© NXP B.V. 2010. All rights reserved.
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