C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 232

• Manufacturer Part Number: C8051F700-GQR
• Description: MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-GQR

• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F70x
• Maximum Speed: 25 MHz
• Ram Size: 512 Byte
• Program Memory Size: 15 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 54
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 16-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F70x/71x
30.5. SMBus Transfer Modes
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end
of all SMBus byte frames. The position of the ACK interrupt when operating as a receiver depends on
whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs before the
ACK with hardware ACK generation disabled, and after the ACK when hardware ACK generation is
enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK generation
is enabled or not.
30.5.1. Write Sequence (Master)
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-
ates the START condition and transmits the first byte containing the address of the target slave and the
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by
the slave. The transfer is ended when the STO bit is set and a STOP is generated. The interface will switch
to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt. Figure 30.5
shows a typical master write sequence. Two transmit data bytes are shown, though any number of bytes
may be transmitted. Notice that all of the “data byte transferred” interrupts occur after the ACK cycle in this
mode, regardless of whether hardware ACK generation is enabled.
232
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 30.5. Typical Master Write Sequence
Interrupts with Hardware ACK Disabled (EHACK = 0)
Interrupts with Hardware ACK Enabled (EHACK = 1)
W
A
Data Byte
Rev. 1.0
A
S = START
P = STOP
A = ACK
W = WRITE
SLA = Slave Address
Data Byte
A
P