AT89C5131A-RDTIM Atmel, AT89C5131A-RDTIM Datasheet
AT89C5131A-RDTIM
Related parts for AT89C5131A-RDTIM
AT89C5131A-RDTIM Summary of contents
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Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T0, T1 and T2 – 256 ...
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... Endpoints (EP1/EP2/EP3/EP4/EP5/EP6) with minimum software overhead are also part of the USB module. AT89C5131 retains the features of the Atmel 80C52 with extended Flash capacity (32- Kbyte), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator. ...
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Block Diagram XTAL1 XTAL2 ALE PSEN CPU EA (2) RD (2) WR Notes: 1. Alternate function of Port 1 2. Alternate function of Port 3 3. Alternate function of Port 4 4136C–USB–04/05 (2) (2) EEPROM EUART 32Kx8 Flash 4Kx8 RAM ...
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Pinout Description Pinout AT89C5131 4 Figure 1. AT89C5131 52-pin PLCC Pinout P4.1/SDA 8 P2.3/A11 9 10 P2.4/A12 P2.5/A13 11 12 XTAL2 13 XTAL1 14 P2.6/A14 P2.7/A15 15 VDD 16 AVDD ...
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Figure 2. AT89C5131 64-pin VQFP Pinout P2.3/A11 3 P2.4/A12 4 P2.5/A13 5 XTAL2 6 XTAL1 7 P2.6/A14 8 P2.7/A15 9 VDD 10 AVDD AVSS 13 NC ...
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AT89C5131 6 Figure 3. AT89C5131 48-pin MLF Pinout P4.1/SDA P2.3/A11 2 P2.4/A12 3 P2.5/A13 4 5 XTAL2 6 XTAL1 7 P2.6/A14 P2.7/A15 8 VDD 9 AVDD 10 11 AVSS 12 P3.0/RxD 13 ...
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Signals 4136C–USB–04/05 All the AT89C5131 signals are detailed by functionality on Table 1 through Table 12. Table 1. Keypad Interface Signal Description Signal Name Type Description Keypad Input Lines KIN[7:0) I Holding one of these pins high or low for ...
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AT89C5131 8 Table 4. Timer 0, Timer 1 and Timer 2 Signal Description (Continued) Signal Name Type Description Timer Counter 0 External Clock Input T0 I When Timer 0 operates as a counter, a falling edge on the T0 pin ...
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Table 8. Ports Signal Description Signal Name Type Description Port 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used P0[7:0] I/O as high impedance inputs. ...
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AT89C5131 10 Table 11. System Signal Description Signal Name Type Description Multiplexed Address/Data LSB for external access AD[7:0] I/O Data LSB for Slave port access (used for 8-bit and 16-bit modes) Address Bus MSB for external access A[15:8] I/O Data ...
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Table 12. Power Signal Description (Continued) Signal Name Type Description USB pull-up Controlled Output VREF is used to control the USB D+ 1.5 kΩ pull up. VREF O The Vref output is in high impedance when the bit DETACH ...
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SFR Mapping AT89C5131 12 The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, ...
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Table 13. SFR Descriptions Bit Addressable 0/8 1/9 CH UEPINT F8h 0000 0000 0000 0000 LEDCON B F0h 0000 0000 0000 0000 CL E8h 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 00X0 0000 00XX X000 FCON (1) PSW ...
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AT89C5131 14 The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories: Table 14. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register Program Status PSW D0h Word Stack Pointer SP 81h LSB ...
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Table 16. Timer SFR’s Mnemonic Add Name TH0 8Ch Timer/Counter 0 High byte TL0 8Ah Timer/Counter 0 Low byte TH1 8Dh Timer/Counter 1 High byte TL1 8Bh Timer/Counter 1 Low byte TH2 CDh Timer/Counter 2 High byte TL2 CCh Timer/Counter ...
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Table 19. PCA SFR’s Mnemo- nic Add Name CCON D8h PCA Timer/Counter Control CMOD D9h PCA Timer/Counter Mode CL E9h PCA Timer/Counter Low byte CH F9h PCA Timer/Counter High byte CCAPM0 DAh PCA Timer/Counter Mode 0 CCAPM1 DBh PCA Timer/Counter ...
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Table 22. Keyboard SFRs Mnemonic Add Name Keyboard Flag KBF 9Eh Register Keyboard Input Enable KBE 9Dh Register Keyboard Level KBLS 9Ch Selector Register Table 23. TWI SFRs Mnemonic Add Name Synchronous Serial SSCON 93h Control Synchronous Serial SSCS 94h ...
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Table 25. USB SFR’s Mnemonic Add Name UEPDATX CFh USB Endpoint X FIFO Data USB Byte Counter Low (EP UBYCTLX E2h X) USB Byte Counter High UBYCTHX E3h (EP X) UFNUML BAh USB Frame Number Low UFNUMH BBh USB Frame ...
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Clock Controller Introduction Figure 5. Oscillator Block Diagram X1 X2 EXT48 PD PLLCON.2 PCON.1 Oscillator 4136C–USB–04/05 The AT89C5131 clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals ...
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PLL PLL Description Figure 7. PLL Block Diagram and Symbol N divider OSC N3:0 CLOCK AT89C5131 20 Figure 6. Crystal Connection VSS The AT89C5131 PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external ...
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PLL Programming Divider Values 4136C–USB–04/05 The PLL is programmed using the flow shown in Figure 9. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable. Figure ...
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Registers AT89C5131 22 Table 28. CKCON0 (S:8Fh) Clock Control Register WDX2 PCAX2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. Watchdog ...
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Table 29. CKCON1 (S:AFh) Clock Control Register Bit Bit Number Mnemonic Description Reserved 7-1 - The value read from this bit is always 0. Do not set this bit. SPI Clock This ...
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Dual Data Pointer Register Figure 10. Use of Dual Pointer 7 0 DPS AUXR1(A2H) AT89C5131 24 The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by ...
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ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 ...
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... Figure 12 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 33 describes the external memory interface signals. volt- DD FFFFh 32 Kbytes External Code 8000h 7FFFh 32 Kbytes Flash 0000h AT89C5131A 4136C–USB–04/05 ...
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External Bus Cycles 4136C–USB–04/05 Figure 12. External Code Memory Interface Structure AT89C5130A/ AT89C5131 P2 ALE AD7:0 P0 PSEN Table 33. External Data Memory Interface Signals Signal Name Type Description Address Lines A15:8 O Upper address lines for the external bus. ...
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... Architecture Figure 14. Flash Memory Architecture Hardware Security (1 Byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 3FFFh for AT89C5130A for 16 KB 7FFFh for AT89C5131A for 32 KB FM0 Memory Architecture User Space Extra Row (XRow) Hardware Security Space Column Latches AT89C5131 28 AT89C5131 features two on-chip Flash memories: • ...
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Overview of FM0 Operations Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column Launching Programming 4136C–USB–04/05 The CPU interfaces to the Flash memory through the FCON register and AUXR1 ...
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Status of the Flash Memory Selecting FM0/FM1 AT89C5131 30 The Flash memory enters a busy state as soon as programming is launched. In this state, the memory is not available for fetching code. Thus to avoid any erratic execution during ...
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Loading the Column Latches Programming the Flash Spaces User 4136C–USB–04/05 Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page ...
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Extra Row AT89C5131 32 The following procedure is used to program the Extra Row space and is summarized in Figure 16: • Load data in the column latches from address FF80h to FFFFh. • Disable the interrupts. • Launch the ...
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Hardware Security 4136C–USB–04/05 The following procedure is used to program the Hardware Security space and is sum- marized in Figure 17: • Set FPS and map Hardware byte (FCON = 0x0C) • Disable the interrupts. • Load DPTR at address ...
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Reading the Flash Spaces User Extra Row Hardware Security AT89C5131 34 The following procedure is used to read the User space and is summarized in Figure 18: • Map the User space by writing 00h in FCON register. • Read ...
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Registers 4136C–USB–04/05 Table 36. FCON (S:D1h) Flash Control Register FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command Bits 7-4 FPL3:0 Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table ...
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Flash EEPROM Memory General Description Features Flash Programming and Erasure 4136C–USB–04/05 The Flash memory increases EPROM functionality with in-circuit electrical erasure and programming. It contains 16/32 Kbytes of program memory organized in 256 pages of 128 bytes, respectively. This memory ...
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Flash Registers and Memory Map Hardware Registers Bootloader Jump Bit (BLJB) Flash Memory Lock Bits AT89C5131 36 The AT89C5131 Flash memory uses several registers: • Hardware registers can only be accessed through the parallel programming modes which are handled by ...
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... Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. These values are used by Atmel ISP (see Section “In-Sys- tem Programming (ISP)”). These registers are in the “Extra Flash Memory” part of the Flash memory. This block is also called ” ...
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... Do not clear this bit. User Memory Lock Bits 1-0 LB1-0 See Table 41 Default value FCh – 1011 1000b – 0FFh – FFh – 58h Atmel C51 X2, Electrically D7h Erasable F7h AT89C5131 32 Kbyte FBh AT89C5131 16 Kbyte AT89C5131 32 Kbyte, EFh revision 0 AT89C5131 16 Kbyte, FFh revision 0 4 ...
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... Flash Memory Status Figure 19. Flash Memory Possible Contents 3FFFh AT89C5130A 7FFFh AT89C5131A Virgin 0000h Default After ISP Memory Organization 4136C–USB–04/05 The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown to Table 41. ...
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EEPROM Data Memory Description Write Data in the Column Latches Programming Read Data AT89C5131 40 The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh of the ERAM memory space and is selected by setting control bits ...
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Registers 4136C–USB–04/05 Table 42. EECON (S:0D2h) EECON Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. Reserved 3 - The ...
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... There are three methods for programming the Flash memory: • The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the USB. API can be called also by user’s bootloader located in FM0 at [SBV]00h. • ...
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... This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F400h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro- gramming. -To read or modify this bit, the APIs are used. ...
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... Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All these APIs are described in detail in the following document on the Atmel web site. – Datasheet Bootloader USB AT89C5131. ...
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Hardware Security Byte 4136C–USB–04/05 Table 44. Hardware Security Byte X2B BLJB OSCON1 Bit Bit Number Mnemonic Description X2 Bit 7 X2B Set this bit to start in standard mode Clear this bit to start in X2 mode. ...
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On-chip Expanded RAM (ERAM) Figure 22. Internal and External Data Memory Address 0FFh or 3FFh ERAM 00 AT89C5131 46 The AT89C5131 provides additional Bytes of random access memory (RAM) space for increased data parameter handling and high level language usage. ...
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When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. • Instructions ...
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AT89C5131 48 Table 46. AUXR Register AUXR - Auxiliary Register (8Eh DPU - M0 Bit Bit Number Mnemonic Description Disable Weak Pull Up 7 DPU Cleared to enabled weak pull up on standard Ports. Set to disable ...
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... The Auto-reload mode configures Timer 16-bit timer or event counter with auto- matic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel 8-bit microcontroller hardware description). If DCEN bit is set, Timer 2 acts as an Up/down timer/counter as shown in Figure 23. In this mode the T2EX pin controls the direction of count ...
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Figure 23. Auto-reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH Programmable Clock Output AT89C5131 C/T2 T2CON (DOWN COUNTING RELOAD VALUE) FFh (8-bit) (8-bit) TL2 (8-bit) (8-bit) RCAP2L RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) In ...
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It is possible to use Timer baud rate generator and a clock generator simulta- neously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H ...
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AT89C5131 52 Table 47. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on Timer ...
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Table 48. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Programmable Counter Array (PCA) AT89C5131 54 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as ...
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Figure 25. PCA Timer/Counter F /6 CLK PERIPH F /2 CLK PERIPH T0 OVF P1.2 Idle 4136C–USB–04/05 CIDL CPS1 CPS0 WDTE CF CR CCF4 CCF3 CCF2 CCF1 CCF0 Table 49. CMOD Register CMOD - PCA Counter Mode Register (D9h) 7 ...
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AT89C5131 56 The CMOD register includes three additional bits associated with the PCA (See Figure 25 and Table 49). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE bit enables or disables the watchdog ...
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Figure 26. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 ECF 4136C–USB–04/05 The watchdog timer function is implemented in module 4 (See Figure 28). The PCA interrupt system is shown in Figure ...
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AT89C5131 58 the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the ...
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Table 52. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn There are two additional registers ...
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AT89C5131 60 Table 53. CCAPnH Registers (n = 0-4) CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh) CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh) CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh) CCAP3H ...
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PCA Capture Mode Figure 27. PCA Capture Mode CF Cex.n ECOMn 16-bit Software Timer/Compare Mode 4136C–USB–04/05 Table 56. CL Register CL - PCA Counter Register Low (0E9h Bit Bit Number Mnemonic Description PCA Counter ...
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Figure 28. PCA Compare Mode and PCA Watchdog Timer Write to CCAPnL Reset Write to CCAPnH Enable 1 0 High Speed Output Mode AT89C5131 62 CCF4 CF CR CCAPnH CCAPnL Match 16-bit Comparator CH CL PCA Counter/Timer ECOMn CAPPn CAPNn ...
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Figure 29. PCA High-speed Output Mode Write to Reset CCAPnL Write to CCAPnH 0 Enable 1 Pulse Width Modulator Mode 4136C–USB–04/ CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16-bit Comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn ...
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PCA Watchdog Timer AT89C5131 64 Figure 30. PCA PWM Mode Overflow Enable ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog ...
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Serial I/O Port Framing Error Detection 4136C–USB–04/05 The serial I/O port in the AT89C5131 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and ...
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Automatic Address Recognition Given Address AT89C5131 66 Figure 33. UART Timings in Modes 2 and 3 RXD D0 D1 Start Bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 The automatic address recognition feature is enabled ...
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Broadcast Address Reset Addresses 4136C–USB–04/05 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t care bit; for slaves B and C, bit ...
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Baud Rate Selection for UART for Mode 1 and 3 Baud Rate Selection Table for UART Internal Baud Rate Generator (BRG) AT89C5131 68 SADDR - Slave Address Register (A9h Reset Value = 0000 0000b Not bit addressable ...
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Figure 35. Internal Baud Rate CLK PERIPH BRR 4136C–USB–04/05 auto reload counter 0 /6 BRG 1 BRL SPD • The baud rate for UART is token by formula: Baud_Rate = (BRL) = 256 - 2 ...
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AT89C5131 70 Table 57. SCON Register – SCON Serial Control Register (98h FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid ...
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UART Registers 4136C–USB–04/05 Example of computed value when SMOD1 = 1, SPD = 16.384 MHz OSCA Baud Rates BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Example ...
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AT89C5131 72 BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah – – – Reset Value = 0000 0000b Table 58. T2CON Register T2CON - Timer 2 Control Register (C8h ...
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Table 59. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 for UART 7 SMOD1 Set to select double baud rate in mode 1, ...
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AT89C5131 74 Table 60. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit ...
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Interrupt System Overview Figure 36. Interrupt Control System INT0 TF0 INT1 TF1 PCA TF2 EXF2 KBD IT TWI IT SPI IT USBINT UEPINT Individual Enable 4136C–USB–04/05 The AT89C5131 has a total of 15 interrupt vectors: two external ...
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Registers AT89C5131 76 Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register (Table 62). This register also contains a global disable bit, which must be cleared ...
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Table 62. IEN0 Register IEN0 - Interrupt Enable Register (A8h ET2 Bit Bit Number Mnemonic Description Enable All interrupt bit 7 EA Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt ...
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AT89C5131 78 Table 63. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...
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Table 64. IPH0 Register IPH0 - Interrupt Priority High Register (B7h PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...
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AT89C5131 80 Table 65. IEN1 Register IEN1 - Interrupt Enable Register (B1h EUSB - Bit Bit Number Mnemonic Description 7 - Reserved USB Interrupt Enable bit 6 EUSB Cleared to disable USB interrupt. Set to enable ...
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Table 66. IPL1 Register IPL1 - Interrupt Priority Register (B2h PUSBL - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. USB Interrupt ...
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AT89C5131 82 Table 67. IPH1 Register IPH1 - Interrupt Priority High Register (B3h PUSBH - Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. ...
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Interrupt Sources and Vector Addresses 4136C–USB–04/05 Table 68. Vector Table Polling Interrupt Number Priority Source 0 0 Reset 1 1 INT0 2 2 Timer INT1 4 4 Timer UART 6 7 Timer 2 7 ...
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Keyboard Interface Introduction Description Interrupt AT89C5131 84 The AT89C5131 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These ...
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Power Reduction Mode Registers 4136C–USB–04/05 P1 inputs allow exit from idle and power down modes as detailed in section “Power- down Mode”. Table 69. KBF Register KBF - Keyboard Flag Register (9Eh KBF7 KBF6 KBF5 Bit Bit ...
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AT89C5131 86 Table 70. KBE Register KBE - Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable ...
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Table 71. KBLS Register KBLS-Keyboard Level Selector Register (9Ch KBLS7 KBLS6 KBLS5 Bit Bit Number Mnemonic Description Keyboard line 7 Level Selection bit 7 KBLS7 Cleared to enable a low level detection on Port line 7. ...
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Programmable LED AT89C5131 88 AT89C5131 have programmable LED current sources, configured by the regis- ter LEDCON. Table 72. LEDCON Register LEDCON (S:F1h) LED Control Register LED3 LED2 Bit Bit Number Mnemonic Description Port/LED3 Configuration ...
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Serial Peripheral Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) 4136C–USB–04/05 The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communication between the MCU and ...
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Baud Rate AT89C5131 90 pins (Figure 39). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission Master configuration, the SS line can be used ...
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Functional Description Operating Modes 4136C–USB–04/05 Figure 40 shows a detailed structure of the SPI module. Figure 40. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request The ...
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Master Mode Slave Mode Transmission Formats AT89C5131 92 Figure 41. Full-duplex Master/Slave Interconnection 8-bit Shift Register SPI Clock Generator Master MCU The SPI operates in Master mode when the Master bit, MSTR is set. Only one Master SPI device can ...
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Figure 42. Data Transmission Format (CPHA = 0) SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture point Figure 43. Data Transmission Format (CPHA = 1) ...
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Error Conditions Mode Fault (MODF) Write Collision (WCOL) Overrun Condition Interrupts AT89C5131 94 The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin ...
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Registers Serial Peripheral Control Register (SPCON) 4136C–USB–04/05 Figure 45. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SSDIS There are three registers in the module that provide control, status and data storage functions. These registers are describes ...
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Serial Peripheral Status Register (SPSTA) AT89C5131 96 Bit Number Bit Mnemonic Description SPR2 SPR1 2 SPR1 SPR0 Reset Value = 0001 0100b Not ...
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Serial Peripheral Data Register (SPDAT) 4136C–USB–04/05 Bit Bit Number Mnemonic Description Reserved 2 - The value read from this bit is indeterminate. Do not set this bit Reserved 1 - The value read from this bit is indeterminate. Do not ...
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Two Wire Interface ( TWI Introduction AT89C5131 98 ) The Synchronous Serial Link Controller (SSLC) provides the selection of one synchro- nous serial interface among the two most popular ones: • Two Wire Interface (TWI). • Serial Peripheral Interface (SPI) ...
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Figure 47. Block Diagram Input Filter SDA PI2.1 Output Stage Input Filter SCL PI2.0 Output Stage 4136C–USB–04/05 SSADR Address Register Comparator SSDAT Shift Register Arbitration and Sink Logic Timing and Control Logic Serial clock generator Timer 1 overflow SSCON Control ...
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Description Figure 48. Complete Data Transfer on TWI Bus SDA SCL S start condition AT89C5131 100 The CPU interfaces to the TWI logic via the following four 8-bit special function regis- ters: the Synchronous Serial Control register (SSCON; Table 85 ...
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Master Transmitter Mode Master Receiver Mode 4136C–USB–04/05 A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition In Figure 49 to Figure 52, circles are used to indicate ...
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Slave Receiver Mode Slave Transmitter Mode AT89C5131 102 SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to Table . After a repeated START condition (state 10h) SSLC may switch to the master transmitter ...
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Miscellaneous States Notes 4136C–USB–04/05 If the AA bit is reset during a transfer, SSLC will transmit the last byte of the transfer and enter state C0h or C8h. SSLC is switched to the not addressed slave mode and will ignore ...
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Figure 49. Format and State in the Master Transmitter Mode Successfull S SLA transmission to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data ...
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Table 80. Status in Master Transmitter Mode Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+W been transmitted Write SLA+W A repeated START 10h condition has been ...
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Figure 50. Format and State in the Master Receiver Mode Successfull transmission S SLA to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or ...
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Table 81. Status in Slave Receiver Mode Status Status of the Two- Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT A START condition has 08h Write SLA+R been transmitted Write SLA+R A repeated START 10h condition has been ...
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Figure 51. Format and State in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave ...
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Table 82. Status in Slave Receiver Mode Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Own SLA+W has been 60h received; ACK has been returned Arbitration lost in SLA+R/W as master; own SLA+W has been 68h received; ...
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Table 82. Status in Slave Receiver Mode (Continued) Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START ...
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Figure 52. Format and State in the Slave Transmitter Mode Reception of the S own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave ...
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Table 83. Status in Slave Transmitter Mode (Continued) Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Data byte in SSDAT has been C0h transmitted; NOT ACK has been received Last data byte in SSDAT has C8h been ...
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Registers 4136C–USB–04/05 Table 85. SSCON Register SSCON - Synchronous Serial Control Register (93h CR2 SSIE STA Bit Bit Number Mnemonic Description Control Rate bit 2 7 CR2 See . Synchronous Serial Interface Enable bit 6 SSIE Clear ...
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AT89C5131 114 Bit Bit Number Mnemonic Description 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Table 87. SSCS (094h) Read - Synchronous Serial Control and Status Register 7 6 ...
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USB Controller Introduction USB Mass Storage Classes USB Mass Storage Class CBI Transport USB Mass Storage Class Bulk- only Transport AT89C5131 114 The AT89C5131 implements a USB device controller supporting full speed data transfer in accordance with the USB 1.1 ...
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USB Device Firmware Upgrade (DFU) Description Figure 53. USB Device Controller Block Diagram D+ USB D+/D- Buffer D- 4136C–USB–04/05 The USB Device Firmware Update (DFU) protocol can be used to upgrade the on-chip Flash memory of the AT89C5131. This allows ...
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Serial Interface Engine (SIE) Figure 54. SIE Block Diagram End of Packet Detection Start of Packet Detection D+ D- Clk48 (48 MHz) AT89C5131 116 The SIE performs the following functions: • NRZI data encoding and decoding. • Bit stuffing and ...
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Function Interface Unit (FIU) Figure 55. UFI Block Diagram FIU DPLL SIE Figure 56. Minimum Intervention from the USB Device Firmware OUT Transactions: OUT DATA0 (n bytes) HOST UFI C51 IN Transactions: IN HOST UFI NACK C51 Endpoint FIFO write ...
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Configuration General Configuration Endpoint Configuration Figure 57. Endpoint Selection UEPSTA0 Endpoint 0 UBYCTH0 UEPSTA6 Endpoint 6 UBYCTH6 AT89C5131 118 • USB controller enable Before any USB transaction, the 48 MHz required by the USB controller must be correctly generated (See ...
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Endpoint enable Before using an endpoint, this one will be enabled by setting the EPEN bit in the UEPCONX register. An endpoint which is not enabled won’t answer to any USB request. The Default Control Endpoint (Endpoint 0) ...
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Read/Write Data FIFO Read Data FIFO Write Data FIFO FIFO Mapping Figure 58. Endpoint FIFO Configuration UEPSTA0 Endpoint 0 UBYCTH0 UEPSTA6 Endpoint 6 UBYCTH6 AT89C5131 120 • Endpoint FIFO reset Before using an endpoint, its FIFO will be reset. This ...
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Bulk/Interrupt Transactions Bulk/Interrupt OUT Transactions in Standard Mode 4136C–USB–04/05 Bulk and Interrupt transactions are managed in the same way. Figure 59. Bulk/Interrupt OUT transactions in Standard Mode HOST OUT DATA0 (n bytes) OUT DATA1 OUT DATA1 DATA1 OUT An endpoint ...
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Bulk/Interrupt OUT Transactions in Ping-pong Mode AT89C5131 122 Figure 60. Bulk/Interrupt OUT Transactions in Ping-pong Mode HOST OUT DATA0 (n Bytes) ACK DATA1 (m Bytes) OUT ACK OUT DATA0 (p Bytes) ACK An endpoint will be first enabled and configured ...
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Bulk/Interrupt IN Transactions in Standard Mode 4136C–USB–04/05 Figure 61. Bulk/Interrupt IN Transactions in Standard Mode UFI HOST IN NAK IN DATA0 (n Bytes) ACK An endpoint will be first enabled and configured before being able to send Bulk or Inter- ...
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Bulk/Interrupt IN Transactions in Ping-pong Mode AT89C5131 124 Figure 62. Bulk/Interrupt IN Transactions in Ping-pong Mode HOST UFI IN NACK IN DATA0 (n Bytes) ACK TXCMPL IN DATA1 (m Bytes) ACK TXCMPL IN DATA0 (p Bytes) ACK An endpoint will ...
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Control Transactions Setup Stage Data Stage: Control Endpoint Direction Status Stage 4136C–USB–04/05 The DIR bit in the UEPSTAX register will Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in ...
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Isochronous Transactions Isochronous OUT Transactions in Standard Mode Isochronous OUT Transactions in Ping-pong Mode AT89C5131 126 An endpoint will be first enabled and configured before being able to receive Isochro- nous packets. When a OUT packet is received on an ...
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Isochronous IN Transactions in Standard Mode Isochronous IN Transactions in Ping-pong Mode 4136C–USB–04/05 If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet ...
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Miscellaneous USB Reset STALL Handshake Start of Frame Detection Frame Number Data Toggle Bit AT89C5131 128 The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been detected on the USB bus. This ...
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Suspend/Resume Management Suspend Resume 4136C–USB–04/05 The Suspend state can be detected by the USB controller if all the clocks are enabled and if the USB controller is enabled. The bit SPINT is set by hardware when an idle state is ...
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Upstream Resume Figure 64. Example of REMOTE WAKEUP Management SET_FEATURE: DEVICE_REMOTE_WAKEUP Detection of a SUSPEND State Upstream RESUME Sent AT89C5131 130 A USB device can be allowed by the Host to send an upstream resume for Remote Wake Up purpose. ...
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Detach Simulation Figure 66. Disconnect Timing D+ V (min) IHZ USB Interrupt System Interrupt System Priorities D+ USB Controller D- 4136C–USB–04/05 In order to be re-enumerated by the Host, the AT89C5131 has the possibility to ...
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USB Interrupt Control System AT89C5131 132 Table 89. Priority Levels IPHUSB IPLUSB shown in Figure 68, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (see Table 96 on page 139). This ...
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Figure 68. USB Interrupt Control Block Diagram Endpoint 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 UEPSTAX.6 RXSETUP UEPSTAX.2 STLCRC UEPSTAX.3 WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 4136C–USB–04/05 EPXINT ...
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USB Registers AT89C5131 134 Table 90. USBCON Register USBCON (S:BCh) USB Global Control Register USBE SUSPCLK SDRMWUP Bit Number Bit Mnemonic Description USB Enable Set this bit to enable the USB controller. 7 USBE Clear this bit ...
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Table 91. USBINT Register USBINT (S:BDh) USB Global Interrupt Register WUPCPU Bit Bit Number Mnemonic Description Reserved 7-6 - The value read from these bits is always 0. Do not set these bits. Wake ...
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AT89C5131 136 Table 92. USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register EWUPCPU Bit Number Bit Mnemonic Description Reserved 7-6 - The value read from these bits is always 0. Do not set these ...
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Table 94. UEPNUM Register UEPNUM (S:C7h) USB Endpoint Number Bit Number Bit Mnemonic Description Reserved 7-4 - The value read from these bits is always 0. Do not set these bits. Endpoint Number ...
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AT89C5131 138 Table 95. UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register EPEN - - Bit Bit Number Mnemonic Description Endpoint Enable Set this bit to enable the endpoint according to the device configuration. 7 EPEN ...
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Table 96. UEPSTAX (S:CEh) USB Endpoint X Status Register 7 6 DIR RXOUTB1 Bit Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h) ...
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AT89C5131 140 Table 97. UEPDATX Register UEPDATX (S:CFh) USB FIFO Data Endpoint EPNUM set in UEPNUM Register UEPNUM (S:C7h FDAT7 FDAT6 FDAT5 Bit Bit Number Mnemonic Description Endpoint X FIFO data FDAT 7 - ...
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Table 99. UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register EPNUM set in UEPNUM Register UEPNUM Bit Number Bit Mnemonic Description Reserved 7-2 - The value read from these ...
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AT89C5131 142 Table 100. UEPRST Register UEPRST (S:D5h) USB Endpoint FIFO Reset Register EP6RST EP5RST Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this ...
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Table 101. UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register EP6INT EP5INT Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this bit. ...
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AT89C5131 144 Table 102. UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register EP6INTE EP5INTE Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is always 0. Do not set this ...
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Table 103. UFNUMH Register UFNUMH (S:BBh, read-only) USB Frame Number High Register CRCOK Bit Bit Number Mnemonic Description Frame Number CRC OK This bit is set by hardware when a new Frame Number in ...
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Power Management Idle Mode Power-down Mode AT89C5131 146 An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off ...
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Figure 69. Power-down Exit Waveform INT0 INT1 XTALA or XTALB Active Phase 4136C–USB–04/05 Power-down Phase Oscillator restart Phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from ...
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Registers AT89C5131 148 Table 106. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial Port Mode bit 1 7 SMOD1 Set to select double baud rate in mode 1, 2 ...
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Hardware Watchdog Timer Using the WDT 4136C–USB–04/05 The WDT is intended as a recovery method in situations where the CPU may be sub- jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) ...
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WDT During Power-down and Idle AT89C5131 150 Table 108. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h Bit Bit Number Mnemonic Description Reserved 5 - The value read from ...
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ONCE Mode (ON Chip Emulation) 4136C–USB–04/05 The ONCE mode facilitates testing and debugging of systems using AT89C5131 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the AT89C5131; the following sequence must ...
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Reduced EMI Mode AT89C5131 152 The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to ...
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Electrical Characteristics Absolute Maximum Ratings Ambient Temperature Under Bias industrial ........................................................-40°C to 85°C Storage Temperature .................................... -65° 150°C Voltage on V from V ...................................-0. 3. Voltage on Any Pin from V .....................-0.5V ...
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Symbol Parameter V Power Fail Low Level Threshold PFDM Power fail hysteresis V PFDP Notes: 1. Operating I is measured with all output pins disconnected; XTAL1 driven with 0.5V 0.5V; XTAL2 ...
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LED’s Table 111. LED Outputs DC Parameters Symbol Parameter I Output Low Current, P3.6 and P3.7 LED modes OL Note -20°C to +50° 4136C–USB–04/05 Figure 71. I Test Condition, Idle Mode ...
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USB DC Parameters AT89C5131 156 BUS GND 3 2 USB “B” Receptacle 1.5 kΩ 27Ω pad Symbol Parameter V USB Reference ...
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AC Parameters Explanation of the AC Symbols External Program Memory Characteristics 4136C–USB–04/05 Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of ...
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AT89C5131 158 Table 113. AC Parameters for a Fix Clock ( MHz) Symbol T T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ Table 114. ...
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External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 External Data Memory Characteristics 4136C–USB–04/ CLCL T T LHLL LLIV T LLPL T PLPH T LLAX T PLIV T T AVLL TPLAZ ...
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AT89C5131 160 Table 116. AC Parameters for a Variable Clock ( MHz) Symbol T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLWL T AVWL T QVWX T QVWH T WHQX T ...
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External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 4136C–USB–04/05 Table 117. AC Parameters for a Variable Clock Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max ...
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External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing - Shift Register Mode AT89C5131 162 T LLDV T LLWL T AVDV T LLAX A0-A7 T RLAZ T AVWL ADDRESS A8-A15 OR ...
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Shift Register Timing Waveform INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms 4136C–USB–04/ ...
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Clock Waveforms STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST ...
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Flash Memory 4136C–USB–04/05 Table 122. Timing Symbol Definitions Signals S (Hardware PSEN, EA Condition) R RST B FBUSY Flag Table 123. Memory AC Timing VDD = 3.3V ± 10 -40 to +85°C A Symbol Parameter T Input PSEN ...
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USB AC Parameters V CRS Differential Data Lines AT89C5131 166 Rise Time 90% 90% 10 Table 124. USB AC Parameters Symbol Parameter t Rise Time R t Fall Time F t Full-speed Data Rate FDRATE V Crossover Voltage ...
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... Ordering Information Table 125. Possible Order Entries Memory Size Part Number AT89C5130A-RDTUM AT89C5130A-PUTUM AT89C5130A-S3SUM AT89C5131A-RDTIM AT89C5131A-PUTIM AT89C5131A-S3SIM AT89C5131A-RDTUM Note: 1. “Green” product version. Green products are delivered in Dry Pack. 2. Optional Packing and Package options (please consult Atmel sales representative) -Tape and Reel ...
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Packaging Information 64-lead VQFP AT89C5131 168 4136C–USB–04/05 ...
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PLCC 4136C–USB–04/05 AT89C5131 169 ...
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QFN Datasheet Change Log Changes from 4337A - 10/04 to 4337B - 12/04 AT89C5131 170 1. Added 16 Kbytes version of Product. 4136C–USB–04/05 ...
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Table of Contents 4136C–USB–04/05 Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ....................................................................................... 3 Pinout Description ................................................................................ 4 Pinout.................................................................................................................... 4 Signals ...................................................................................................................7 SFR Mapping ....................................................................................... 12 Clock Controller .................................................................................. 19 Introduction ......................................................................................................... 19 Oscillator............................................................................................................. 19 PLL ..................................................................................................................... 20 Registers..............................................................................................................22 Dual ...
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Application-Programming-Interface .................................................................... 44 XROW Bytes....................................................................................................... 44 Hardware Conditions .......................................................................................... 44 Hardware Security Byte ...................................................................................... 45 On-chip Expanded RAM (ERAM) ....................................................... 46 Timer 2 ................................................................................................. 49 Auto-reload Mode ............................................................................................... 49 Programmable Clock Output .............................................................................. 50 Programmable Counter Array (PCA) ................................................ ...
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USB Controller .................................................................................. 114 Introduction ....................................................................................................... 114 Description........................................................................................................ 115 Configuration .................................................................................................... 118 Read/Write Data FIFO ...................................................................................... 120 Bulk/Interrupt Transactions............................................................................... 121 Control Transactions......................................................................................... 125 Isochronous Transactions..................................................................................126 Miscellaneous ....................................................................................................128 Suspend/Resume Management ........................................................................129 Detach Simulation..............................................................................................131 USB Interrupt System ....................................................................................... 131 USB Registers ...
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