IS43DR16128-3DBL ISSI, Integrated Silicon Solution Inc, IS43DR16128-3DBL Datasheet - Page 6

• Manufacturer Part Number: IS43DR16128-3DBL
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS43DR16128-3DBL

• Lead Free Status / Rohs Status: Supplier Unconfirmed

IS43/46DR16128
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal
operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically
re‐enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must occur
before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait
for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.
Extended Mode Register 1(EMR[1]) Diagram
Notes:
1.
2.
DDR2 Extended Mode Register 2 (EMR[2]) Setting
The extended mode register 2 controls refresh related features. The default value of the extended mode register 2 is not defined.
Therefore, the extended mode register must be programmed during initialization for proper operation. The extended mode register
2 is written by asserting LOW on CS, RAS, CAS, WE, BA0, BA2, and HIGH on BA1, while controlling pins A0‐A13. The DDR2 SDRAM
should be in all bank precharge state with CKE already HIGH prior to writing into extended mode register 2. The mode register set
command cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register 2. Mode register
contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in
precharge state.
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00B, 3/28/2011
Address
Field
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
When Adjust mode is issued, AL from previously set value must be applied.
After setting to default, OCD calibration mode needs to be exited by setting A9‐A7 to 000.
Program
Register
Additive
Latency
Mode
DQS#
Qoff
OCD
D.I.C
DLL
Rtt
Rtt
0
0
1
0
0
A12
A10
A9
A5
A1
0
1
0
1
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
A8
A4
0
0
1
0
1
0
0
1
1
0
0
1
1
Output buffer enabled
Ouput buffer disabled
Output Drive Impedance Control
Disable
Enable
DQS#
Normal Strength (100%)
Reduced strength (60%)
Qoff
A7
A3
0
1
0
0
1
0
1
0
1
0
1
0
1
Additive Latency
Strobe Function
DQS
DQS
DQS
OCD Calibration mode exit; maintain setting
Reserved
Matrix
0
1
2
3
4
5
6
DQS#
DQS#
Hi‐Z
OCD Calibration default
OCD Calibration Program
Adjust mode
Drive(1)
Drive(0)
(1)
A6
A0
(2)
0
0
1
1
0
1
A2
0
1
0
1
DLL enable
Disable
Enable
Rtt(NOMINAL)
ODT Disabled
150 ohms
75 ohms
50 ohms
6