USB3500-ABZJ Standard Microsystems (SMSC), USB3500-ABZJ Datasheet
USB3500-ABZJ
Specifications of USB3500-ABZJ
Related parts for USB3500-ABZJ
USB3500-ABZJ Summary of contents
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... Supports Host Negotiation Protocol (HNP) and Session Request protocol (SRP.) Internal comparators support OTG monitoring of VBUS levels. Low Latency Hi-Speed Receiver (43 Hi-Speed clocks Max) SMSC USB3500 USB3500 Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface Internal 1.8 volt regulators allow operation from a single 3 ...
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... USB3500-ABZJ FOR 56 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...
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... Universal Serial Bus Specification, Revision 2.0, April 27, 2000 USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000 On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a, June 24, 2003 UTMI+ Specification, Revision 1.0, February 2, 2004 SMSC USB3500 3 DATASHEET Revision 1.0 (06-05-08) ...
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... Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 3 Pin Configuration and Pin Definitions 3.1 USB3500 Pin Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Pin Definitions Chapter 4 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 6 Detailed Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 8bit Bi-Directional Data Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 TX Logic ...
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... Figure 7.7 Resume Timing Behavior (HS Mode Figure 7.8 Device Attach Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 7.9 USB Reset and Chirp Figure 7.10 USB3500 Application Diagram (Top View Figure 8.1 USB3500-ABZJ 56 Pin QFN Package Outline 0.9 mm Body (Lead Free SMSC USB3500 5 DATASHEET Revision 1.0 (06-05-08) ...
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... List of Tables Table 3.1 USB3500 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.3 Recommended External Clock Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5.1 DC Electrical Characteristics: Supply Pins (Note Table 5.2 Electrical Characteristics: CLKOUT Start- Table 5.3 DC Electrical Characteristics: Logic Pins Table 5 ...
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... Datasheet Chapter 1 General Description The USB3500 is a stand-alone Hi-Speed USB Physical Layer Transceiver (PHY). The USB3500 uses a UTMI+ interface to connect to an SOC or FPGA or custom ASIC. The USB3500 provides a flexible alternative to integrating the analog PHY block for new designs. SOC/FPGA/ASIC Including Device Controller ...
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... FS, LS, preamble packet) USB2.0 Peripheral, host controllers, On- (HS, FS, and LS but no preamble packet) USB2.0 Peripheral, host controllers, and 1.1 Applications The USB3500 is targeted for any application where a hi-speed USB connection is desired. The USB3500 is well suited for: Cell Phones MP3 Players Scanners Printers ...
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... Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface Datasheet Chapter 2 Functional Overview The USB3500 is a highly integrated USB transceiver system. It contains a complete USB 2.0 PHY with the UTMI+ industry standard interface to support fast time to market for a USB controller. The USB3500 is composed of the functional blocks shown in Internal VDD3 ...
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... Chapter 3 Pin Configuration and Pin Definitions The USB3500 is offered pin QFN package. The pin definitions and locations are documented below. 3.1 USB3500 Pin Locations 1 VSS 2 XCVRSEL0 TERMSEL 3 4 TXREADY 5 VBUS SUSPENDN TXVALID 8 9 RESET 10 VDD3 VSS 14 VDD3.3 The flag of the QFN package must be connected to ground with a via array. ...
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... TXREADY 5 VBUS SUSPENDN 8 TXVALID 9 RESET 10 VDD3 SMSC USB3500 Table 3.1 USB3500 Pin Definitions ACTIVE TYPE LEVEL DESCRIPTION Ground N/A PHY ground. Input N/A Transceiver Select. These signals select between the FS and HS transceivers: Transceiver select. 00: HS 01: FS 10: LS 11: LS data, FS rise/fall times ...
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... Table 3.1 USB3500 Pin Definitions (continued) DIRECTION, PIN NAME VSS 14 VDD3.3 15 XCVRSEL[1] 16 CHRGVBUS 17 RXACTIVE 18 OPMODE[1] 19 OPMODE[0] 20 ID_DIG 21 IDPULLUP 22 VSS 23 CLKOUT 24 VSS 25 LINESTATE[1] 26 LINESTATE[0] 27 VDD1.8 Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface ACTIVE TYPE LEVEL DESCRIPTION I/O, N/A D- pin of the USB cable ...
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... Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface Datasheet Table 3.1 USB3500 Pin Definitions (continued) DIRECTION, PIN NAME 28 VDD3.3 29 HOSTDISC 30 DISCHRGVBUS 31 SESSEND 32 DATA[7] 33 DATA[6] 34 DATA[5] 35 DATA[4] 36 DATA[3] 37 DATA[2] 38 DATA[1] 39 DATA[0] 40 VSS 41 RXVALID 42 SESSVLD SMSC USB3500 ACTIVE TYPE LEVEL DESCRIPTION N/A N/A 3 ...
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... Table 3.1 USB3500 Pin Definitions (continued) DIRECTION, PIN NAME 43 DPPD 44 DMPD 45 RXERROR 46 VSS 47 VBUSVLD 48 VDD3.3 49 VDD1.8 50 VSS VDDA1.8 54 VDD3.3 55 VDD3.3 56 RBIAS GND FLAG Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface ACTIVE TYPE LEVEL DESCRIPTION Input N/A DP Pull-down Select ...
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... Ambient Temperature T A Table 4.3 Recommended External Clock Conditions PARAMETER SYMBOL System Clock Frequency System Clock Duty Cycle SMSC USB3500 Table 4.1 Maximum Guaranteed Ratings CONDITIONS CONDITIONS CONDITIONS XI driven by the external clock; and no connection driven by the external clock; and no connection at XO ...
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... SS A CONDITIONS MIN = 0V +70C; unless otherwise specified CONDITIONS MIN 8mA -8mA V OH DD3.3 - 0 +70C; unless otherwise specified DATASHEET Datasheet TYP MAX UNITS 60.5 mA 57.5 mA 60.6 mA 62 TYP MAX UNITS 2.25 3.5 ms TYP MAX UNITS 0 DD3.3 0 ± SMSC USB3500 ...
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... HS Data Signaling Common V CMHS Mode Voltage Range HS Squelch Detection Threshold (Differential) V HSSQ Output Levels Hi-Speed Low Level V HSOL Output Voltage (DP/DM referenced to GND) SMSC USB3500 CONDITIONS MIN | V(DP) - V(DM) | 0.2 0.8 2.0 0.050 Pull-up resistor on DP 1.5kΩ DD3.3 Pull-down resistor on DP, 2.8 DM ...
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... IDLE state 500 500 Eye pattern of Template 1 in USB 2.0 specification Eye pattern of Template 4 in USB 2.0 specification Eye pattern of Template 4 in USB 2.0 specification 18 DATASHEET Datasheet TYP MAX UNITS 440 1100 mV -500 mV ± TYP MAX UNITS 2.0 V 111 SMSC USB3500 ...
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... Vbus Pull-down R VbusPd Vbus Impedance R Vbus ID pull-up resistance R IdPullUp ID pull-up resistance R Id SMSC USB3500 = 0V +70C; unless otherwise specified CONDITIONS Output Delay. Measured from PHY output to the rising edge of CLKOUT Setup Time. Measured from PHY input to the rising edge of CLKOUT. Hold time. Measured from ...
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... Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface = 0V +70C; unless otherwise specified SS A Table 5.8 Regulator Output Voltages CONDITIONS Normal Operation (SUSPENDN = 1) Low Power mode (SUSPENDN = +70C; unless otherwise specified DATASHEET Datasheet MIN TYP MAX UNITS 1.6 1.8 2 1.6 1.8 2.0 V SMSC USB3500 ...
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... Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface Datasheet Chapter 6 Detailed Functional Description Figure 2.1 on page 9 shows the functional block diagram of the USB3500. Each of the functions is described in detail below. 6.1 8bit Bi-Directional Data Bus Operation The USB3500 supports an 8-bit bi-directional parallel interface. ...
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... After the Link asserts TXVALID it can assume that the transmission has started when it detects TXREADY has been asserted. The Link must assume that the USB3500 has consumed a data byte if TXREADY and TXVALID are asserted on the rising edge of CLKOUT. The Link must have valid packet information (PID) asserted on the DATA bus coincident with the assertion of TXVALID ...
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... USB3500 will negate RXVALID for one clock cycle, thus skipping a byte time. When the EOP is detected the USB3500 will negate RXACTIVE and RXVALID. After the EOP has been stripped, the USB3500 will begin looking for the next packet. ...
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... Figure 6.5 Receive Timing for a Handshake Packet (no CRC) Figure 6.6 Receive Timing for Setup Packet Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface 24 DATASHEET Datasheet SMSC USB3500 ...
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... Termination Resistors The USB3500 transceiver fully integrates all of the USB termination resistors. The USB3500 includes two 1.5kΩ pull-up resistors on DP and DM and a 15kΩ pull-down resistor on both DP and DM. In addition the 45Ω high speed termination resistors are also integrated. These integrated resistors require no tuning or trimming by the Link ...
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... DATASHEET Datasheet RESISTOR SETTINGS SMSC USB3500 ...
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... The USB3500 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is used by the PHY during both transmit and receive. The USB3500 requires a clean 24MHz crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly ...
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... Power On Reset (POR) The USB3500 provides an internal POR circuit that generates a reset pulse once the PHY supplies are stable. The UTMI+ Digital can be reset at any time with the RESET pin. 6.7 USB On-The-Go (OTG) Module The USB3500 provides support for USB OTG. This mode allows the USB3500 to be dynamically configured as a host or a device depending on the type of cable inserted into the Mini-AB connector ...
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... A B PERIPHERAL The USB3500 provides an integrated pull-up resistor to pull the ID pin to VDD3.3 when a Mini-B plug is inserted and the cable is floating. When a Mini-A plug is connected, the pull-up resistor will be overpowered and the ID pin will be brought to ground. To save current when a Mini-A Plug is inserted, the ID pull-up resistor can be disabled by clearing the IDPULLUP pin ...
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... The OTG Supplement requires an A-Device that supports Session request protocol to have an input impedance less than 100kohm and greater the 40kohm to ground. In addition, if configured Device, the PHY cannot draw more then 150uA from Vbus. The USB3500 provides a 75kΩ nominal resistance to ground which meets the above requirements. ...
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... The HS receiver is used to detect Chirp where the output of the HS receiver is always qualified with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the USB3500 alternative to using variable thresholds for the single-ended receivers, the following approach is used device mode, 3ms of no USB activity (IDLE state) signals a reset. The Link monitors LINESTATE[1:0] for the IDLE state ...
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... When using OPMODE[1:0] = 10, the SYNC and EOP patterns are not transmitted. The only exception to this is when OPMODE[1:0] is set to 10 while TXVALID has been asserted (the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the USB3500 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also be transmitted to properly terminate the packet ...
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... FS mode after bus activity stops. T2 Link samples LINESTATE. If LINESTATE = SE0, then the SE0 on the bus is due to a Reset state. The device now enters the HS Detection Handshake protocol. SMSC USB3500 DESCRIPTION 0 (reference) HS Reset 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100µs < T2 < ...
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... Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface DESCRIPTION 0 (reference) HS Reset 0ms < T1 < HS Reset T0 + 3.125ms T1 + 100 µs < T2 < 875µs HS Reset T0 + 5ms HS Reset T0 + 10ms 34 DATASHEET Datasheet VALUE SMSC USB3500 ...
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... This transceiver design pushes as much of the responsibility for timing events on to the Link as possible, and the Link requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3 above, CLKOUT has been running and is stable, however in case 1 the USB3500 is reset from a suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered down ...
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... The Link must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration. Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface DESCRIPTION 0 (reference) T0 < T1 < HS Reset T0 + 6.0ms T1 + 1.0 ms < T2 < HS Reset T0 + 7.0ms T2 < T3 < T2+100µ 1.0ms < T4 < 2.5ms HS Reset T0 + 10ms 36 DATASHEET Datasheet VALUE SMSC USB3500 ...
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... LINESTATE = J State. The Link must employ a counter (Chirp Count) to count the number of Chirp K and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus state must be “continuously asserted for 2.5µs” must be verified by the Link sampling the LINESTATE signals. SMSC USB3500 !K K State Detect K? ...
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... Table 7.8 Reset Timing Values DESCRIPTION 0 (reference) T0 < T1 < HS Reset T0 + 6.0ms T0 + 1.0ms < T2 < HS Reset T0 + 7.0ms T2 < T3 < T2+100µ 40µs < T4 < 60µ 40µs < T5 < 60µ < T7 < 500µ 500µs < T8 < 100µs HS Reset T0 + 10ms 38 DATASHEET Datasheet VALUE SMSC USB3500 ...
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... OPMODE 0 OPMODE 1 XCVRSELECT TERMSELECT SUSPENDN TXVALID CLK60 DP/DM J Figure 7.6 HS Detection Handshake Timing Behavior from Suspend SMSC USB3500 Figure 7.6 shows how CLKOUT is used to control the duration of the for completion of the High Speed Handshake SE0 CLK power up time Device Chirp K 39 DATASHEET Section 7.9, " ...
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... Figure 7.7 Resume Timing Behavior (HS Mode) Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface DESCRIPTION 40 DATASHEET Datasheet }, the Link must see FILT VALUE 0 (HS Reset T0) T0 < T1 < 5.6ms T1 < T2 < 5.8ms T2 + 1.0 ms < T3 < 7 < T3 < 20.0ms SMSC USB3500 ...
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... HS Device Attach Figure 7.8 demonstrates the timing of the USB3500 control signals during a device attach event. When a HS device is attached to an upstream port, power is asserted to the device and the device sets XCVRSELECT and TERMSELECT to FS mode (time T1 the +5V power available on the USB cable. Device Reset in BUS within normal operational range as defined in the USB 2 ...
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... T2 Debounce interval. The device now enters the HS Detection Handshake protocol. (HS Reset T0) Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface Figure 7.8 Device Attach Behavior DESCRIPTION 42 DATASHEET Datasheet VALUE 0 (reference 100ms < 100ms < T2 SMSC USB3500 ...
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... Figure 7.9 shows the UTMI+ interface for both a Host (DPPD & DMPD = 1) and a Device (DPPD & DMPD = 0). The following discussion applies to when the USB3500 is a configured as a Device and is connected to another USB3500 configured as a Host. Since the Host and Device negotiate this transition, both are discussed together and the user may follow this discussion for either a host or device depending on the application of the USB3500. This sequence is also referred “ ...
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... At T8, the Host sends the first SOF packet. This is done by putting the SOF PID 0xA5 on the data bus and asserting Txvalid. The link transfers the SOF packet. After, the SOF packet a normal high speed USB session started. Revision 1.0 (06-05-08) Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface 44 DATASHEET Datasheet SMSC USB3500 ...
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... XCVRSEL0 TERMSEL 5 Volt TXREADY VBUS Supply C VBUS Host Only SUSPENDN TXVALID USB RESET ID Connector VDD3.3 DP (Standard or Mini) DM VDD3.3 Figure 7.10 USB3500 Application Diagram (Top View) SMSC USB3500 C LOAD VBUS 5 ID USB3500 6 Hi-Speed USB 7 UTMI+ PHY 8 56 Pin QFN GND FLAG ...
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... Chapter 8 Package Outline The USB3500 is offered in a compact 56 lead QFN package. Figure 8.1 USB3500-ABZJ 56 Pin QFN Package Outline 0.9 mm Body (Lead Free) Table 8.1 56 Terminal QFN Package Parameters MIN NOMINAL A 0. 0.60 A3 0.20 REF D 7.85 D1 7.55 D2 2.25 E 7.85 E1 7.55 E2 2. ...