FC-255 32.7680K-A0 Epson, FC-255 32.7680K-A0 Datasheet
FC-255 32.7680K-A0
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FC-255 32.7680K-A0 Summary of contents
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MF1225-01 SED1797D Series 0B ...
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Overview ·································································································································································· 1 Features ··································································································································································· 1 Block Diagram ·························································································································································· 2 Bump Layout ···························································································································································· 3 Bump Coordinates ··················································································································································· 4 Functions of Pins ····················································································································································· 7 Operations ······························································································································································· 9 Shift Data Transfer ············································································································································· 9 Gate Output ····················································································································································· 10 Timing Chart ···················································································································································· 10 Absolute ...
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... Develop design and implementation methods to achieve a light-shielding IC structure in actual op- eration. (2) For the inspection process, prepare an environment where the light-shielding feature of the IC can be tested (3) Light-shielding design should include considerations ON OFF for light-shielding features of the front and backside surfaces as well as side faces of the IC. EPSON SED1797 D Series 0B 1 ...
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... SED1797 D Series 0B Block Diagram OFF V DDH CPV DIO1 SHL XOE XRES DIO2 2 O1 O240 Gate output circuit: 240 bits Level shifter Control logic Two-way shift register EPSON ...
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... Shipping form: Chip size: Wafer thickness: Bump shape: Bump height (general standard) Deviation of bump height (within a chip): Bump hardness: Bump size (0,0) Chip (X) 17.1 mm (Y) 1.1 mm 625 m Straight wall Range (Unit: m) Pin X Y Input 88 80 Output 45 80 Tolerance EPSON SED1797 D Series ...
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... O19 7112.8 94 O20 7048.8 95 O21 6984.8 96 O22 6920.8 97 O23 6856.8 98 O24 6792.8 99 O25 6728.8 100 O26 6664.8 EPSON Unit: m Signal X Y No. Name coordinate coordinate 101 O27 6600.8 423.0 102 O28 6536.8 103 O29 6472.8 104 O30 6408.8 105 O31 6344.8 106 O32 6280 ...
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... O152 –2632.8 245 O153 –2696.8 246 O154 –2760.8 247 O155 –2824.8 248 O156 –2888.8 249 O157 –2652.8 250 O158 –3016.8 EPSON SED1797 D Series 0B Unit: m Signal X Y No. Name coordinate coordinate 251 O159 –3080.8 423.0 252 O160 –3144.8 253 O161 –3208.8 254 O162 – ...
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... O229 –7560.8 322 O230 –7624.8 323 O231 –7688.8 324 O232 –7752.8 325 O233 –7816.8 326 O234 –7880.8 327 O235 –7944.8 328 O236 –8008.8 329 O237 –8072.8 330 O238 –8136.8 331 O239 –8200.8 332 O240 –8264.8 333 DUMMY –8356.0 6 EPSON ...
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... XOE="V " voltage output OFF CC XOE="V " : Normal output status SS " resets data in all the shift registers. The gate SS " level. OFF " level. EE " level. EE EPSON SED1797 D 0B Number of Pins DIO1 DIO2 O240 Input Output O240 Output Input 1 1 ...
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... Test pin for internal logic power supply. Set it to "OPEN." Dummy bump Auxiliary bump for COG implementation. Electrically "OPEN." DUMMY N/A 8 Function OFF ON DDH OFF ON DDH DDH OFF DDH EPSON Number of Pins 240 TBD TBD TBD TBD TBD TBD 1 TBD ...
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... GND Controller side Shift Direction Data Output Pin O1.O2 ······ O239.O240 O240.O239 ······ O2.O1 V DDH Gate Output V ON Logic input OFF V EE Driver side EPSON SED1797 D Series 0B DIO2 DIO1 DIO output 9 ...
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... If the reset pin is not used, inputting 240 clocks clears data in all the shift registers with shift data input fixed to the “L” level. Note, however, gate output during this initialization period becomes indefinite. Timing Chart Case: SHL = “V ” (reference example CPV XRES DIO1 XOE O240 DIO2 10 3 EPSON ” voltage is applied for gate OFF 239 240 OFF ...
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... V , always maintain the relation and V that the relations OFF OFF becomes 0.7V or under as well. These conditions may affect reliability of the IC DDH OFF EPSON SED1797 D Rating Unit –0.3 to +7.0 V –0.3 to +45.0 V –23.0 to +0.3 V –0.3 to +45.0 V +0.3 V DDH –0 –40 to +85 C – ...
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... OFF f CPV OFF power voltage, maintain the relation V OFF DDH 15[V] V – V DDH 5.5[ 6.8[ –V [V] DDH EE EPSON = 0V) Rating Unit +1.8 to +5.5 V +10.0 to +30.0 V –20.0 to –5.0 V +15.0 to +40 200 kHz at the same potential as that – 15[V]. In this case, EE OFF ON 40[V] V 25.5[ ...
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... EES Dynamic current consumption ( Dynamic current consumption ( Dynamic current consumption ( Dynamic current consumption ( *1: SHL= "H", XRES="H", DIO1=CPV=XOE="L", DIO2="OPEN", no load on the output pins. *2: VGA display, fCPV=36 kHz, fDIO=75 Hz, no load on the output pins. (Ta= – Rating Condition MIN. TYP 0 –V ...
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... RS Resetting process (Ta=– =3.3 0.3V Symbol Condition CL=20pF tpd1 tpd2 tpd3 CL=220pF V =30V tpd4 ON V =10V tpd5 OFF tpd6 EPSON =0V, V =30V, V =–10V) SS DDH EE MIN. MAX. Unit s 5.0 s 0.9 s 0.9 300 ns 300 ns s 1.0(*2) s 5.0(*2) s 1.0(*3) 50% Resetting process is completed ...
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... CPV 50% DIO (IN) DIO (OUT) tpd3 90% 50 XOR On t CPV 50% 50 CPVH CPVL 50% tpd4 90% 50% 10 WOE 50% 50% tpd5 tpd6 50% 50% EPSON SED1797 D Series 0B 50% 50% tpd1 tpd2 50% 50% 15 ...