ISL8200MEVAL1PHZ Intersil, ISL8200MEVAL1PHZ Datasheet - Page 5

• Manufacturer Part Number: ISL8200MEVAL1PHZ
• Description: EVAL BAORD FOR ISL8200
• Manufacturer: Intersil
• Series: -r

Specifications of ISL8200MEVAL1PHZ

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: 0.6 ~ 6 V
• Current - Output: 10A
• Voltage - Input: 3 ~ 20 V
• Regulator Topology: Buck
• Frequency - Switching: 700kHz ~ 1.5MHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL8200
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Pin Descriptions
Typical Application Circuits
NUMBER
GND
PIN
PD1
PD2
PD3
PD4
VIN
21
22
23
Thermal Pad
V
Thermal Pad
Thermal Pad
PIN NAME
IN
PGOOD
Phase
PGND
V
VCC
Thermal
Pad
NC
OUT
R1
16.5k
R2
4.12k
* Select R1 & R2
0.8V<V
such that
EN
Analog Input - This pin provides bias power for the analog circuitry. It’s operational range is 2.97V to
5.6V. In 3.3V applications, VCC, PVCC and VIN should be shorted to allow operation at the low end
input as it relates to the V
regulator or by an external voltage source.
Analog Output - Provides an open drain Power Good signal when the output is within 9% of nominal
output regulation point with 4% hysteresis (13%/9%), and soft-start is complete. PGOOD monitors the
outputs (VMON1) of the internal differential amplifiers. Output Voltage Range: 0V to V
Not internal connected
Used for both the PHASE pin (Pin # 16) and for heat removal connecting to heat dissipation layers using
Vias. Potential should be floating and not electrically connected to anything except PHASE pin 16.
Used for both the PVIN pin (Pin # 17) and for heat removal connecting to heat dissipation layers using
Vias. Potential should be floating and not electrically connected to anything except VPVIN pin 17.
Used for both the PGND pin (Pin # 18) and for heat removal connecting to heat dissipation layers using
Vias. Potential should be floating and not electrically connected to anything except PGND pin 18.
Used for both the VOUT pin (Pin # 19) and for heat removal connecting to heat dissipation layers using
Vias. Potential should be floating and not electrically connected to anything except VOUT pin 19.
<5.0V
CIN(CER)
5
CEN
1nF
(Continued)
FIGURE 3. SINGLE PHASE 10A 1.2V OUTPUT CIRCUIT
ISF ETDRV1
RISHARE
5k
U201
ISL8200M
PVIN
VIN
FF
EN
FSYNC_IN
CLKOUT
ISHARE_BUS
ISFETDRV
CC
falling threshold limit. This pin can be powered either by the internal linear
ISL8200M
PIN DESCRIPTION
VSEN_REM-
PH_CNTRL
VOUT_SET
PGOOD
VOUT
VCC
10uF
CPVCC
PGOOD1
2.2k
RSET
VOUT
(See Table 1,
V
OUT
CC
- R
February 26, 2010
COUT
.
SET
on page 13)
FN6727.1
GND