SAF-XC164CS-16F40FBB Infineon Technologies, SAF-XC164CS-16F40FBB Datasheet - Page 68
SAF-XC164CS-16F40FBB
Manufacturer Part Number
SAF-XC164CS-16F40FBB
Description
Manufacturer
Infineon Technologies
Datasheet
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4.4.2
The XC164CS’s Flash module delivers data within a fixed access time (see
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
available speed grade as well as on the actual system frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
Table 17
Parameter
Flash module access time
Programming time per 128-byte block
Erase time per sector
1) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), devices can be
operated with 1 waitstate: ((1+1) × 25 ns) ≥ 50 ns.
Table 18
Table 18
Required Waitstates
0 WS (WSFLASH = 00
1 WS (WSFLASH = 01
Note: The maximum achievable system frequency is limited by the properties of the
Data Sheet
t
ACC
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
respective derivative, i.e. 40 MHz (or 20 MHz for xxx-16F20F devices).
indicates the interrelation of waitstates and system frequency.
of the Flash array. Therefore, the required Flash waitstates depend on the
On-chip Flash Operation
Flash Characteristics (Operating Conditions apply)
Flash Access Waitstates
B
B
)
)
66
Symbol
t
t
t
ACC
PR
ER
Frequency Range
f
f
CPU
CPU
CC
CC
CC
≤ 20 MHz
≤ 40 MHz
Min.
–
–
–
Limit Values
Electrical Parameters
Typ.
2
–
200
1)
1)
Max.
50
5
500
Derivatives
V2.3, 2006-08
Table 17
XC164CS
Unit
ns
ms
ms
).
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