PIC18F4680-H/PT Microchip Technology, PIC18F4680-H/PT Datasheet - Page 354

• Manufacturer Part Number: PIC18F4680-H/PT
• Description: IC MCU 8BIT 64KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-H/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
24.2
For PIC18F2585/2680/4585/4680 devices, the WDT is
driven by the INTRC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
INTRC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: a SLEEP or CLRWDT instruction is executed, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
.
FIGURE 24-1:
DS39625C-page 352
Change on IRCF bits
All Device Resets
INTRC Source
Watchdog Timer (WDT)
WDTPS<3:0>
SWDTEN
WDTEN
CLRWDT
Sleep
WDT BLOCK DIAGRAM
Enable WDT
WDT Counter
÷128
INTRC Control
4
Preliminary
Programmable Postscaler
1:1 to 1:32,768
24.2.1
Register 24-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
Configuration bit, but only if the Configuration bit has
disabled the WDT.
Note 1: The CLRWDT and SLEEP instructions
2: Changing the setting of the IRCF bits
3: When a CLRWDT instruction is executed,
WDT
CONTROL REGISTER
clear the WDT and postscaler counts
when executed.
(OSCCON<6:4>) clears the WDT and
postscaler counts.
the postscaler count will be cleared.
Reset
© 2007 Microchip Technology Inc.
Wake-up
from Power
Managed Modes
WDT
Reset