PIC18F4680-H/PT Microchip Technology, PIC18F4680-H/PT Datasheet - Page 138

• Manufacturer Part Number: PIC18F4680-H/PT
• Description: IC MCU 8BIT 64KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-H/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
TABLE 10-5:
DS39625C-page 136
RC0/T1OSO/
T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL RC3
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Legend:
Pin Name
PWR = Power Supply; OUT = Output; IN = Input; ANA = Analog Signal; DIG = Digital Output; ST = Schmitt Buffer Input;
TTL = TTL Buffer Input
RC0
T1OSO
T13CKI
RC1
T1OSI
RC2
CCP1
SCK
SCL
RC4
SDI
SDA
RC5
SDO
RC6
TX
CK
RC7
RX
DT
Function
PORTC I/O SUMMARY
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TRIS
0
1
x
1
0
1
x
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
0
1
1
0
1
1
1
1
I
I
2
2
Buffer
C/SMB I
C/SMB I
ANA
ANA
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
DIG
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Preliminary
LATC<0> data output.
PORTC<0> data input.
Timer1 oscillator output – overrides the TRIS<0> control when enabled.
Timer1/Timer3 clock input.
LATC<1> data output.
PORTC<1> data input.
Timer1 oscillator input – overrides the TRIS<1> control when enabled.
LATC<2> data output.
PORTC<2> data input.
CCP1 compare output.
CCP1 capture input.
LATC<3> data output.
PORTC<3> data input.
SPI clock output (MSSP module) – must have TRIS set to ‘1’ to allow the
MSSP module to control the bidirectional communication.
SPI clock input (MSSP module).
I
allow the MSSP module to control the bidirectional communication.
LATC<4> data output.
PORTC<4> data input.
SPI data input (MSSP module).
I
allow the MSSP module to control the bidirectional communication.
the MSSP module to control the bidirectional communication.
LATC<5> data output.
PORTC<5> data input.
SPI data output (MSSP module).
LATC<6> data output.
PORTC<6> data input.
EUSART data output.
EUSART synchronous clock output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
EUSART synchronous clock input.
LATC<7> data output.
PORTC<7> data input.
EUSART asynchronous data input.
EUSART synchronous data output – must have TRIS set to ‘1’ to enable
EUSART to control the bidirectional communication.
EUSART synchronous data input.
2
2
2
2
C™/SM bus clock output (MSSP module) – must have TRIS set to ‘1’ to
C/SM bus clock input.
C/SM bus data output (MSSP module) – must have TRIS set to ‘1’ to
C/SM bus data input (MSSP module) – must have TRIS set to ‘1’ to allow
Description
© 2007 Microchip Technology Inc.