PIC18F2680-H/SP Microchip Technology, PIC18F2680-H/SP Datasheet - Page 50
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F2680-H/SP
Manufacturer Part Number
PIC18F2680-H/SP
Description
IC MCU 8BIT 48KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F4585-IPT.pdf
(482 pages)
Specifications of PIC18F2680-H/SP
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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4.6
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal
operation. Status bits from the RCON register, RI, TO,
PD, POR and BOR, are set or cleared differently in
different Reset situations, as indicated in Table 4-3.
These bits are used in software to determine the nature
of the Reset.
TABLE 4-3:
DS39625C-page 48
Power-on Reset
RESET Instruction
Brown-out
MCLR during Power Managed
Run modes
MCLR during Power Managed
Idle modes and Sleep mode
WDT Time-out during Full Power
or Power Managed Run modes
MCLR during Full Power
Execution
Stack Full Reset (STVREN = 1)
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
WDT Time-out during Power
Managed Idle or Sleep modes
Interrupt Exit from Power
Managed modes
Legend: u = unchanged
Note 1:
2:
Reset State of Registers
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (008h or 0018h).
Reset state is ‘1’ for POR and unchanged for all other Resets when software BOR is enabled
(BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is ‘0’.
Condition
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
PC + 2
Counter
PC + 2
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
(1)
SBOREN
Preliminary
u
u
u
u
u
u
u
u
u
u
u
1
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
RCON Register
RI
Table 4-4 describes the Reset states for all of the
Special Function Registers. These are categorized by
Power-on and Brown-out Resets, Master Clear and
WDT Resets and WDT wake-ups.
1
0
1
u
u
u
u
u
u
u
u
u
TO
1
u
1
1
1
0
u
u
u
u
0
u
PD
1
u
1
u
0
u
u
u
u
u
0
0
POR BOR STKFUL
0
u
u
u
u
u
u
u
u
u
u
u
© 2007 Microchip Technology Inc.
0
u
0
u
u
u
u
u
u
u
u
u
STKPTR Register
0
u
u
u
u
u
u
1
u
u
u
u
STKUNF
0
u
u
u
u
u
u
u
1
1
u
u
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