PIC18F1220-H/P Microchip Technology, PIC18F1220-H/P Datasheet - Page 229

• Manufacturer Part Number: PIC18F1220-H/P
• Description: IC MCU 8BIT 4KB FLASH 18PDIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1220-H/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SUBLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
W
C
W
C
Z
N
W
C
W
C
Z
N
W
C
W
C
Z
N
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
literal ‘k’
Subtract W from literal
[ label ] SUBLW k
0 ≤ k ≤ 255
k – (W) → W
N, OV, C, DC, Z
W is subtracted from the eight-bit
literal ‘k’. The result is placed
in W.
1
1
SUBLW
SUBLW
SUBLW
Read
Q2
0000
1
?
1
1
0
0
2
?
0
1
1
0
3
?
FF ; (2’s complement)
0
0
1
; result is positive
; result is zero
; result is negative
0x02
0x02
0x02
1000
Process
Data
Q3
kkkk
Write to W
Q4
kkkk
SUBWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example 1:
Example 2:
Example 3:
Q Cycle Activity:
Before Instruction
After Instruction
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
REG
W
C
REG
W
C
Z
N
PIC18F1220/1320
Q1
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ‘f’
Subtract W from f
[ label ] SUBWF
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) – (W) → dest
N, OV, C, DC, Z
Subtract W from register ‘f’ (2’s
complement method). If ‘d’ is ‘0’,
the result is stored in W. If ‘d’ is
‘1’, the result is stored back in
register ‘f’ (default). If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ is
‘1’, then the bank will be selected
as per the BSR value (default).
1
1
SUBWF REG
SUBWF REG, W
SUBWF REG
Read
Q2
0101
3
2
?
1
2
1
0
0
2
2
?
2
0
1
1
0
0x01
0x02
?
0xFFh ;(2’s complement)
0x02
0x00
0x00
0x01
; result is positive
; result is zero
;result is negative
11da
Process
Data
Q3
DS39605F-page 227
ffff
f [,d [,a]]
destination
Write to
Q4
ffff