PIC18F1220-H/P Microchip Technology, PIC18F1220-H/P Datasheet - Page 224

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PIC18F1220-H/P

Manufacturer Part Number
PIC18F1220-H/P
Description
IC MCU 8BIT 4KB FLASH 18PDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet

Specifications of PIC18F1220-H/P

Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
18-DIP (0.300", 7.62mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC18F1220/1320
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39605F-page 222
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
Status
GIE/GIEH, PEIE/GIEL
Q1
No
operation
operation
Return from Interrupt
[ label ]
s ∈ [0,1]
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged.
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
1
2
RETFIE
0000
Q2
No
No
1
RETFIE [s]
0000
operation
operation
=
=
=
=
=
Q3
No
No
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
operation
Pop PC
GIEL
Q4
No
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
W
W
Q1
No
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to W
[ label ]
0 ≤ k ≤ 255
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
None
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
1
2
literal ‘k’
Read
0000
Q2
No
0x07
value of kn
© 2007 Microchip Technology Inc.
RETLW k
1100
operation
Process
Data
Q3
No
kkkk
from stack,
Write to W
operation
Pop PC
Q4
No
kkkk

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