PIC16LF1933-I/MV Microchip Technology, PIC16LF1933-I/MV Datasheet - Page 88

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PIC16LF1933-I/MV

Manufacturer Part Number
PIC16LF1933-I/MV
Description
IC MCU 8BIT 7KB FLASH 28UQFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet

Specifications of PIC16LF1933-I/MV

Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-UFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16LF1933-I/MV
Manufacturer:
MICROCHIP
Quantity:
4 500
Part Number:
PIC16LF1933-I/MV
Manufacturer:
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PIC16(L)F1933
7.6.3
The PIE2 register contains the interrupt enable bits, as
shown in
REGISTER 7-3:
DS41575A-page 88
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W-0/0
OSFIE
Register
PIE2 REGISTER
OSFIE: Oscillator Fail Interrupt Enable bit
1 = Enables the oscillator fail interrupt
0 = Disables the oscillator fail interrupt
C2IE: Comparator C2 Interrupt Enable bit
1 = Enables the comparator C2 interrupt
0 = Disables the comparator C2 interrupt
C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the comparator C1 interrupt
0 = Disables the comparator C1 interrupt
EEIE: EEPROM Write Completion Interrupt Enable bit
1 = Enables the EEPROM write completion interrupt
0 = Disables the EEPROM write completion interrupt
BCLIE: MSSP Bus Collision Interrupt Enable bit
1 = Enables the MSSP bus collision Interrupt
0 = Disables the MSSP bus collision Interrupt
LCDIE: LCD Module Interrupt Enable bit
1 = Enables the LCD module interrupt
0 = Disables the LCD module interrupt
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
7-3.
R/W-0/0
C2IE
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
C1IE
R/W-0/0
EEIE
Preliminary
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCLIE
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
R/W-0/0
LCDIE
 2011 Microchip Technology Inc.
U-0
R/W-0/0
CCP2IE
bit 0

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