ISL23328TFVZ-TK Intersil, ISL23328TFVZ-TK Datasheet - Page 8

• Manufacturer Part Number: ISL23328TFVZ-TK
• Description: IC DGTL POT 2CH 100K 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23328TFVZ-TK

• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Interface Specification
NOTES:
10. FS error = [V(RW)
11. DNL = [V(RW)
12. INL = [V(RW)
13.
14. MI =
15. Roffset = RW
16. RDNL = (RW
18.
19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
20. It is preferable to ramp up both the V
21. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
22. RMATCH = (RWi,x - RWi,y)/MI, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
17. RINL = [RW
7. Typical values are for T
8. LSB = [V(RW)
9. ZS error = V(RW)
SYMBOL
TC
TC
t
t
voltage when changing from one tap to an adjacent tap.
hex respectively.
Roffset = RW
first followed by the V
t
t
t
HD:DAT
HD:STO
HD:STA
SU:DAT
SU:STO
t
t
HD:A
t
SU:A
Cb
V
R
DH
t
t
R
F
=
|
=
RW
Max V RW
----------------------------------------------------------------------------- -
[
------------------------------------------------------ -
Max Ri
127
i
(
i
– (MI • i) – RW
i
Ri +25°C
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
STOP Condition Set-up Time
STOP Condition Hold Time for Read
or Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
A2, A1, A0 Setup Time
A2, A1, A0 Hold Time
127
0
127
– RW
(
i
– i • LSB – V(RW)
– RW
V RW
(
/
– V(RW)
(
MI, when measuring between RW and RL.
(
0
) Min Ri
/
– V(RW)
127
/
MI, when measuring between RW and RH.
–
LSB.
i-1
)
0
i
i
|
) Min V RW
(
)
– V
CC
/
+25°C
A
/
–
i-1
MI -1, for i = 8 to 127.
127. MI is a minimum increment. RW
)
.
= +25°C and 3.3V supply voltages.
PARAMETER
(
CC
]
0
/
]
LSB-1, for i = 1 to 127. i is the DCP register setting.
/
]
0
)
/
127. V(RW)
(
]
LSB.
]
/
)
×
MI, for i = 8 to 127.
8
)
(
0
---------------------
+165°C
]/LSB for i = 1 to 127
10
)
i
LOGIC
6
)
×
127
---------------------
+165°C
10
and the V
and V(RW)
for i = 8 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the
minimum value of the resistance over the temperature range.
6
For SCL, SDA, A0, A1, A2 unless otherwise noted. (Continued)
From SDA falling edge
crossing 30% of V
falling edge crossing 70% of
V
From SDA exiting the 30% to
70% of V
rising edge crossing 30% of
V
From SCL falling edge crossing
70% of V
the 30% to 70% of V
window
From SCL rising edge crossing
70% of V
edge crossing 30% of V
From SDA rising edge to SCL
falling edge; both crossing
70% of V
From SCL falling edge crossing
30% of V
enters the 30% to 70% of
V
I
I
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
Before START condition
After STOP condition
OL
OL
LOGIC
LOGIC
LOGIC
For i = 8 to 127decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage
and Min( ) is the minimum value of the wiper voltage over the temperature range.
CC
= 3mA, V
= 0.5mA, V
0
supplies at the same time. If this is not possible, it is recommended to ramp-up the V
are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental
TEST CONDITIONS
window.
LOGIC
LOGIC
LOGIC
LOGIC
LOGIC
127
ISL23328
LOGIC
, to SDA rising
, until SDA
to SDA entering
LOGIC
window, to SCL
and RW
LOGIC
> 2V.
LOGIC
< 2V
LOGIC
LOGIC
0
LOGIC
to SCL
are the measured resistances for the DCP register set to 7F hex and 00
20 + 0.1 x Cb
20 + 0.1 x Cb
(Note 19)
1300
MIN
600
100
600
600
600
10
0
0
(Note 7)
TYP
(Note 19)
MAX
250
250
400
August 19, 2011
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
pF
ns
ns
FN7902.0
LOGIC