LFE2-50E-5F484I Lattice, LFE2-50E-5F484I Datasheet - Page 73

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LFE2-50E-5F484I

Manufacturer Part Number
LFE2-50E-5F484I
Description
FPGA 48000 CELLS 90NM (CMOS) 1.2
Manufacturer
Lattice
Series
ECP2r
Datasheet

Specifications of LFE2-50E-5F484I

Number Of Logic Elements/cells
48000
Number Of Labs/clbs
6000
Total Ram Bits
396288
Number Of I /o
339
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-BBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q3220905AABC
LatticeECP2/M External Switching Characteristics
t
f
General I/O Pin Parameters (using Primary Clock with PLL)
t
t
Lattice Semiconductor
H_DELE
MAX_IOE
COPLL
SUPLL
Parameter
10
Clock to Data Hold - PIO Input
Register with Input Data Delay
Clock Frequency of I/O and PFU
Register
Clock to Output - PIO Output
Register
Clock to Data Setup - PIO Input
Register
Description
Over Recommended Operating Conditions
LFE2-6
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
ECP2/M
LFE2-6
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
LFE2-6
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
Device
3-22
1
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.80
-7
Max.
2.30
2.30
2.30
2.30
2.30
2.30
2.30
2.30
2.60
2.60
2.70
420
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
9
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.80
0.90
(Continued)
-6
Max.
2.60
2.60
2.60
2.60
2.60
2.60
2.60
2.60
2.90
2.90
3.00
357
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
1.00
-5
Max.
2.80
2.80
2.80
2.80
2.80
2.80
2.80
2.80
3.10
3.10
3.20
311
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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