LFE2-50E-5F484I Lattice, LFE2-50E-5F484I Datasheet - Page 35

• Manufacturer Part Number: LFE2-50E-5F484I
• Description: FPGA 48000 CELLS 90NM (CMOS) 1.2
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-50E-5F484I

• Number Of Logic Elements/cells: 48000
• Number Of Labs/clbs: 6000
• Total Ram Bits: 396288
• Number Of I /o: 339
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-BBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q3220905AABC

Lattice Semiconductor
Figure 2-30. Input Register Block Top Edge
Output Register Block
The output register block provides the ability to register signals from the core of the device before they are passed
to the sysI/O buffers. The blocks on the PIOs on the left, right and bottom contain a register for SDR operation that
is combined with an additional latch for DDR operation. Figure 2-31 shows the diagram of the Output Register
Block for PIOs on the left, right and the bottom edges. Figure 2-32 shows the diagram of the Output Register Block
for PIOs on the top edge of the device.
In SDR mode, ONEG0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-
type or latch. In DDR mode, ONEG0 and OPOS0 are fed into registers on the positive edge of the clock. Then at
the next clock cycle this registered OPOS0 is latched. A multiplexer running off the same clock selects the correct
register for feeding to the output (D0).
By combining the output blocks of the complementary PIOs and sharing some registers from input blocks, a gear-
box function can be implemented, that takes four data streams: ONEG0A, ONEG1A, ONEG1B and ONEG1B.
Figure 2-32 shows the diagram using this gearbox function. For more information about this topic, please see infor-
mation regarding additional documentation at the end of this data sheet.
(from sysIO
DEL[3:0]
routing)
buffer)
CLK0
(from
DI
Note: Simplified version does not show CE and SET/RESET details.
*On selected blocks.
Fixed Delay
Dynamic Delay
2-32
D
/LATCH
D-Type
LatticeECP2/M Family Data Sheet
Q
INCK*
INDD
IPOS0
Architecture