M38517F8FP Renesas Electronics America, M38517F8FP Datasheet - Page 29

• Manufacturer Part Number: M38517F8FP
• Description: MCU 8-Bit 740 CISC 32KB Flash 5V 42-Pin SSOP
• Manufacturer: Renesas Electronics America

Specifications of M38517F8FP

• Package: 42SSOP
• Family Name: 740
• Maximum Speed: 8 MHz
• Ram Size: 1 KB
• Program Memory Size: 32 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 34
• Interface Type: I2C-BUS
• On-chip Adc: 5-chx10-bit
• Operating Temperature: -20 to 85 °C
• Number Of Timers: 4

3851 Group
Fig. 24 Block diagram of Serial I/O2
Fig. 25 Timing chart of Serial I/O2
Rev.1.01
R e c e i v e e n a b l e s i g n a l S
S e r i a l I / O 2 o u t p u t S
P0
P0
P4
P0
T r a n s f e r c l o c k ( N o t e 1 )
N o t e s
P0
S e r i a l I / O 2 i n p u t S
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Oct 15, 2003
1
0
3
3
/S
2
/S
/S
s e r i a l I / O 2 r e g i s t e r
/S
/S
(Built-in 24 KB or more ROM)
W r i t e - i n s i g n a l t o
OUT2
IN2
CMP2
X
RDY2
CLK2
X
CIN
1 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e f ( X
2 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s a t r a n s f e r c l o c k , t h e S
IN
Main clock division ratio
selection bits (Note)
/INT
b y s e t t i n g b i t s 0 t o 2 o f s e r i a l I / O 2 c o n t r o l r e g i s t e r 1 .
Serial I/O2 port selection bit
Serial I/O2 port selection bit
2
Serial I/O2 I/O comparison
signal control bit
O U T 2
R D Y 2
I N 2
page 27 of 89
S
RDY2
P0
“1”
“0”
P0
“0”
“1”
P0
output enable bit
“1”
2
“0”
1
latch
3
latch
latch
“0”
P4
“00”
“01”
“10”
“1”
3
S
latch
RDY2
Synchronous circuit
D
Q
0
Serial I/O2 synchronous
clock selection bit
External clock
D
D
1
.
Optional transfer bits (3)
D
Serial I/O counter 2 (3)
Serial I/O2 register (8)
2
“1”
O U T 2
“0”
I N
1/8
1/16
1/32
1/64
1/128
1/256
) c l o c k d i v i s i o n ( f ( X
p i n h a s h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n .
D
3
D
4
Internal synchronous
clock selection bits
C I N
S e r i a l I / O 2 i n t e r r u p t r e q u e s t b i t s e t
) i n l o w - s p e e d m o d e ) c a n b e s e l e c t e d
D
Data bus
5
D
6
Serial I/O2
interrupt request
D
7
( N o t e 2 )