PALCE22V10Z-25SC Lattice, PALCE22V10Z-25SC Datasheet - Page 2

• Manufacturer Part Number: PALCE22V10Z-25SC
• Description: SPLD PAL® Family 10 Macro Cells 50MHz EECMOS Technology 5V 24-Pin SOIC
• Manufacturer: Lattice

Specifications of PALCE22V10Z-25SC

• Package: 24SOIC
• Family Name: PAL®
• Number Of Macro Cells: 10
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 16
• Re-programmability Support: Yes

BLOCK DIAGRAM
FUNCTIONAL DESCRIPTION
The PALCE22V10 allows the systems engineer to implement the design on-chip, by programming
EE cells to configure AND and OR gates within the device, according to the desired logic function.
Complex interconnections between gates, which previously required time-consuming layout, are
lifted from the PC board and placed on silicon, where they can be easily modified during
prototyping or production.
The PALCE22V10Z is the zero-power version of the PALCE22V10. It has all the architectural features
of the PALCE22V10. In addition, the PALCE22V10Z has zero standby power and unused product
term disable.
Product terms with all connections opened assume the logical HIGH state; product terms
connected to both true and complement of any single input assume the logical LOW state.
The PALCE22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four
potential output configurations registered output or combinatorial I/O, active high or active low
(see Figure 1). The configuration choice is made according to the user’s design specification and
corresponding programming of the configuration bits S
to ground (0) through a programmable bit, selecting the “0” path through the multiplexer. Erasing
the bit disconnects the control line from GND and it is driven to a high level, selecting the “1” path.
The device is produced with an EE cell link at each input to the AND gate array, and connections
may be selectively removed by applying appropriate voltages to the circuit. Utilizing an easily-
implemented programming algorithm, these products can be rapidly programmed to any
customized pattern.
2
RESET
OUTPUT
MACRO
LOGIC
CELL
I/O
8
0
1
OUTPUT
MACRO
LOGIC
CELL
I/O
CLK/I
10
1
0
OUTPUT
MACRO
LOGIC
I/O
CELL
12
2
PALCE22V10 and PALCE22V10Z Families
OUTPUT
MACRO
LOGIC
CELL
I/O
14
3
OUTPUT
PROGRAMMABLE
MACRO
LOGIC
CELL
I/O
16
AND ARRAY
4
(44 x 132)
OUTPUT
MACRO
LOGIC
CELL
I/O
16
5
0
- S
OUTPUT
MACRO
1
LOGIC
I/O
CELL
. Multiplexer controls are connected
14
6
OUTPUT
MACRO
LOGIC
CELL
I/O
12
7
OUTPUT
MACRO
LOGIC
CELL
I/O
11
10
8
I
1
- I
OUTPUT
MACRO
LOGIC
CELL
I/O
11
8
9
PRESET